Một ô SRAM 10 transistor 65 nm chịu được sự cố do sự kiện đơn lẻ

Springer Science and Business Media LLC - Tập 32 - Trang 137-145 - 2016
Yuanqing Li1, Lixiang Li2,3, Yuan Ma2, Li Chen1, Rui Liu1, Haibin Wang1, Qiong Wu4, Michael Newton1, Mo Chen1
1Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, Canada
2Department of Electrical and Computer Engineering, Dalhousie University, Halifax, Canada
3TSMC Design Technology Canada, Kanata, Canada
4College of Information and Control Engineering, China University of Petroleum, Qingdao, China

Tóm tắt

Một ô SRAM mới chịu được sự cố do sự kiện đơn lẻ (SEU) được trình bày trong bài báo này. Bằng cách thêm bốn transistor nữa vào bên trong, mạch đề xuất có thể đạt được điện tích quan trọng cao hơn ở mỗi nút nội bộ so với ô 6 transistor (6T) thông thường. Các mảng dung lượng 2k-bit của hai thiết kế này đã được triển khai trong công nghệ CMOS bulk 65 nm để so sánh. Các thí nghiệm bức xạ cho thấy, ở điện áp nguồn danh nghĩa 1.0 V, ô được đề xuất đạt được mức giảm 47,1 % và 49,3 % trong tỷ lệ lỗi mềm do alpha và proton (SER) với diện tích tăng thêm 37 %.

Từ khóa

#SRAM #sự cố do sự kiện đơn lẻ #transistor #độ mềm của lỗi #công nghệ CMOS 65 nm

Tài liệu tham khảo

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