Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load

Analog Integrated Circuits and Signal Processing - Tập 14 Số 1 - Trang 29-39 - 1997
Adler, Victor1, Friedman, Eby G.1
1Department of Electrical Engineering, University of Rochester, Rochester

Tóm tắt

A delay and power model of a CMOS inverter driving aresistive-capacitive load is presented. The model is derivedfrom Sakurai‘s alpha-power law and exhibits good accuracy. Themodel can be used to design and analyze those CMOS invertersthat drive a large RC load when considering bothspeed and power. Expressions are provided for estimating thepropagation delay and transition time which exhibit less than27% discrepancy from SPICE for a wide variety of RCloads. Expressions are also provided for modeling the short-circuitpower dissipation of a CMOS inverter driving a resistive-capacitiveinterconnect line which are accurate to within 15% of SPICEfor most practical loads.

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