A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS
Tóm tắt
This paper presents a 7.5 GS/s, 4.5 bit flash analog-to-digital converter (ADC) for high-speed backplane communication. A two-stage track-and-hold (T/H) structure enables high input bandwidth and low power consumption at the same time. A sampling clock duty cycle control technique, which allocates more tracking time to the bandwidth-limited second T/H stage, facilitates high sampling rates. A digital offset correction scheme compensates both random and systematic offsets due to process variation and T/H amplifier gain nonlinearity, simultaneously. Two test-chip prototypes were fabricated in a 65 nm CMOS process. Experimental results of a standalone ADC chip demonstrate 3.8 effective number of bits (ENOB) at 7.5 GS/s. The figure-of-merit (FOM) of the standalone ADC is 0.49 pJ/conversion-step. The second test chip combines two ADCs together in order to demonstrate a time-interleaved ADC (TI-ADC) for use in high-speed backplane receivers. The TI-ADC operates at 10.24 GS/s while achieving 3.5 ENOB and 0.65 pJ/conversion-step FOM.
Tài liệu tham khảo
Harwood, M. et al. (2007). A 12.5 Gb/s SerDes in 65 nm CMOS using a baud- rate ADC with digital receiver equalization and clock recovery. IEEE International Solid-State Circuits Conference Digest Technical Papers (pp. 436–437).
Cao, J. et al. (2009). A 500 mW digitally calibrated AFE in 65 nm CMOS for 10 Gb/s serial links over backplane and multimode fiber. IEEE international solid-state circuits conference digest technical papers (pp. 370–371).
Choi, M. et al. (2008). A 6-bit 5-GSample/s Nyquist A/D converter in 65 nm CMOS. IEEE symposium VLSI circuits digest technical papers, pp. 16–17.
Park, S., Palaskas, Y., & Flynn, M. (2007). A 4-GS/s 4-bit Flash ADC in 0.18-μm CMOS. IEEE Journal of Solid-State Circuits, 42(9), 1865–1872.
Chen, V.-C., & Pileggi, L. (2013). An 8.5 mW 5 GS/s 6b flash ADC with dynamic offset calibration in 32 nm CMOS SOI. IEEE symposium VLSI circuits digest technical papers (pp. 264–265).
El-Chammas, M., & Murmann, B. (2010). A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration. IEEE symposium VLSI circuits digest technical papers (pp. 157–158).
Nazemi, A. et al. (2008). A 10.3 GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90 nm CMOS. IEEE symposium VLSI circuits digest technical papers (pp. 18–19).
Zhang, B. et al. (2013). A 195 mW/55 mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40 nm CMOS. IEEE international solid-state circuits conference digest technical papers (pp. 34–35).
Verma, S. et al. (2013). A 10.3 GS/s 6b flash ADC for 10G Ethernet applications. IEEE international solid-state circuits conference digest technical papers (pp. 462-463).
Tabasy, E. et al. (2013). A 6b 10 GS/s TI-SAR ADC with embedded 2-tap FFE/1-tap DFE in 65 nm CMOS. IEEE symposium VLSI circuits digest technical papers (pp. 260–261).
Kull, L. et al. (2013). A 35 mW 8b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32 nm Digital SOI CMOS. IEEE symposium VLSI Circuits digest technical paper (pp. 264–265).
Sundström, T., & Alvandpour, A. (2010). A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS. Journal of Analog Integrated Circuits and Signal Processing, 64(3), 215–222.
Yang, C.-K., & Chen, E.-H. (2009). ADC-based serial I/O receivers. Proceedings IEEE Custom Integrated Circuits Conference (pp. 323–330).
Van der Wagt, J., & Teshome, M. (2001). An 8-GHz bandwidth 1-GS/s GaAs HBT dual track-and-hold. IEEE symposium VLSI circuits digest technical papers (pp 215–216).
Chen, C., Le, M., & Kim, K. (2008) A low power 6-bit flash ADC with reference voltage and common-mode calibration. IEEE symposium VLSI circuits digest technical papers (pp. 12–13).
Flynn, M., Donovan, C., & Sattler, L. (2003). Digital calibration incorporating redundancy of flash ADCs. IEEE Transactions Circuits System II, 50(3), 205–213.
Chung, H., & Wei, G.-Y. (2014). ADC-based backplane receiver design-space exploration. IEEE Transactions on VLSI Systems, 22(7), 1539–1547.