Performance analysis of massively parallel embedded hardware architectures for retinal image processing
Tóm tắt
This paper examines the implementation of a retinal vessel tree extraction technique on different hardware platforms and architectures. Retinal vessel tree extraction is a representative application of those found in the domain of medical image processing. The low signal-to-noise ratio of the images leads to a large amount of low-level tasks in order to meet the accuracy requirements. In some applications, this might compromise computing speed. This paper is focused on the assessment of the performance of a retinal vessel tree extraction method on different hardware platforms. In particular, the retinal vessel tree extraction method is mapped onto a massively parallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate arrays (FPGA).
Tài liệu tham khảo
Bankman I: Handbook of Medical Imaging: Processing and Analysis. Academic Press, London; 2000.
Patton N, Aslam T, MacGillivray T, Deary I, Dhillon B, Eikelboom R, Yogesan K, Constable I: Retinal image analysis: concepts, applications and potential. Prog Retin Eye Res 2006, 25(1):99-127. 10.1016/j.preteyeres.2005.07.001
Lowell J, Hunter A, Steel D, Basu A, Ryder R, Kennedy R: Measurement of retinal vessel widths from fundus images based on 2-D modeling. IEEE Trans Med Imaging 2004, 23: 1196-1204. 10.1109/TMI.2004.830524
Wilson C, Cocker K, Moseley M, Paterson C, Clay S, Schulenburg W, Mills M, Ells A, Parker K, G Quinn, et al.: Computerized analysis of retinal vessel width and tortuosity in premature infants. Investig Ophthalmol Vis Sci 2008, 49(8):3577. 10.1167/iovs.07-1353
Ortiz D, Cubides M, Suarez A, Zequera M, Quiroga J, Gomez J, Arroyo N: System for Measuring the Arterious Venous Rate (AVR) for the Diagnosis of Hypertensive Retinopathy. ANDESCON, 2010 IEEE 2010, 1-4.
Salem N, Nandi A: Unsupervised Segmentation of Retinal Blood Vessels Using a Single Parameter Vesselness Measure. Sixth Indian Conference on Computer Vision, Graphics Image Processing, 2008. ICVGIP '08 2008, 528-534.
Lion N-X, Zagorodnov V, Tan Y-P: Retinal Vessel Detection Using Self-Matched Filtering. IEEE International Conference on Image Processing, 2007. ICIP 2007 2007, 6: VI-33-VI-36.
Li Q, You J, Zhang L, Zhang D, Bhattacharya P: A New Approach to Automated Retinal Vessel Segmentation Using Multiscale Analysis. 18th International Conference on Pattern Recognition, 2006. ICPR 2006 2006, 4: 77-80.
Alonso-Montes C, Vilarino D, Dudek P, Penedo M: Fast retinal vessel tree extraction: A pixel parallel approach. Int J Circuit Theory Appl 2008, 36(5-6):641-651. 10.1002/cta.512
Alonso-Montes C, Ortega M, Penedo M, Vilarino D: Pixel Parallel Vessel Tree Extraction for a Personal Authentication System. IEEE International Symposium on Circuits and Systems. ISCAS 2008 2008, 1596-1599.
MacLean W: An evaluation of the suitability of FPGAs for embedded vision systems (IEEE). Computer Vision and Pattern Recognition-Workshops, 2005. CVP Workshops. IEEE Computer Society Conference on 2005, 131.
Rode H, Chiddarwar A, Darak S: Suitability of FPGA for computationally intensive image processing algorithms. IET Seminar Digests, 2009 2009, 65-65.
Foty D: Perspectives on Scaling Theory and CMOS Technology--Understanding the Past, Present, and Future. Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004 2004, 631-637.
Dally W, Kapasi U, Khailany B, Ahn J, Das A: Stream processors: Programmability and efficiency. Queue 2004, 2(1):52-62. 10.1145/984458.984486
Kass M, Witkin A, Terzopoulos D: Snakes: Active contour models. Int J Comput Vis 1998, 1(4):321-331.
Cohen L, Cohen I: Finite-element methods for active contour models and balloons for 2-D and 3-D images. IEEE Trans Pattern Anal Mach Intell 2002, 15(11):1131-1147.
Vilariño D, Rekeczky C: Pixel-level snakes on the CNNUM: algorithm design, on-chip implementation and applications. Int J Circuit Theory Appl 2005, 33(1):17-51. 10.1002/cta.302
Dudek P, Vilarino L: A Cellular Active Contours Algorithm Based on Region Evolution (IEEE). 10th International Workshop on Cellular Neural Networks and Their Applications, 2006. CNNA 2006 2006, 1-6.
Vilarino D, Dudek P: Evolution of Pixel Level Snakes Towards an Efficient Hardware implementation. IEEE International Symposium on Circuits and Systems, 2007. IS-CAS 2007 2007, 2678-2681.
Staal J, Abramoff M, Niemeijer M, Viergever M, van Ginneken B: Ridge based vessel segmentation in color images of the retina. IEEE Trans Med Imaging 2004, 23(4):501-509. 10.1109/TMI.2004.825627
Rodríguez-Vázquez Á, Domínguez-Castro R, Jiménez-Garrido F, Morillas S, Listán J, Alba L, Utrera C, Espejo S, Romay R: The eye-RIS CMOS vision system. Analog Circuit Design 2008, 15-32.
Paillet F, Mercier D, Bernard T: Second Generation Programmable Artificial Retina. Proceedings of the Twelfth Annual IEEE International ASIC/SOC Conference, 1999 1999, 304-309.
Lopich A, Dudek P: Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array. Int J Circuit Theory Appl 2010, 39: 963-972.
Komuro T, Ishii I, Ishikawa M, Yoshida A: A digital vision chip specialized for high-speed target tracking. IEEE Trans Electron Devices 2003, 50: 191-199. 10.1109/TED.2002.807255
Topol AW, Tulipe DCL, Shi L, Frank DJ, Bernstein K, Steen SE, Kumar A, Singco GU, Young AM, Guarini KW, Ieong M: Three-dimensional integrated circuits. IBM J Res Dev 2006, 50: 491-506.
Kurino H, Nakagawa M, Lee K, Nakamura T, Yamada Y, Park K, Koyanagi M: Smart vision chip fabricated using three dimensional integration technology. Adv Neural Inf Process Syst 2001, 720-726.
Foldesy P, Zarandy A, Rekeczky C, Roska T: 3D Integrated Scalable Focal-Plane Processor Array. 18th European Conference on Circuit Theory and Design, 2007. ECCTD 2007 2007, 954-957.
Dudek P: Implementation of Simd Vision Chip with 128 × 128 Array of Analogue Processing Elements. ISCAS 2005 IEEE International Symposium on Circuits and Systems, 2005 2005, 6: 5806-5809.
Dudek P: A Processing Element for an Analogue SIMD Vision Chip. European Conference on Circuit Theory and Design. ECCTD 2003 2003, 3: 221-224.
Alonso-Montes C, Dudek P, Vilarifio D, Penedo M: On Chip Implementation of a Pixel-Parallel Approach for Retinal Vessel Tree Extraction (IEEE). 18th European Conference on Circuit Theory and Design, 2007. ECCTD 2007 2008, 511-514.
DeHaven K: Extensible Processing Platform Ideal Solution for a Wide Range of Embedded Systems. Extensible Processing Platform Overview White Paper 2010.
Curreri J, Koehler S, Holland B, George A: Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing. 16th International Symposium on Field-Programmable Custom Computing Machines, 2008. FCCM '08 2008, 23-30.
Saegusa T, Maruyama T, Yamaguchi Y: How Fast is an FPGA in Image Processing? International Conference on Field Programmable Logic and Applications, 2008. FPL 2008 2008, 77-82.
Nieto A, Brea V, Vilarino D: FPGA-Accelerated Retinal Vessel-Tree Extraction. International Conference on Field Programmable Logic and Applications, 2009. FPL 2009 2009, 485-488.
Spartan-3 FPGA Family Data Sheet Xilinx Product Specification DS099 2009.
Schroder-Preikschat W, Snelting G: Invasive Computing: An Overview. Multiprocessor System-on-Chip: Hardware Design and Tool Integration 2010, 241.
Butts M, Jones A, Wasson P: A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing. 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2007. FCCM 2007 2007, 55-64.
Hutchings B, Nelson B, West S, Curtis R: Comparing Fine-Grained Performance on the Ambric MPPA Against an FPGA. International Conference on Field Programmable Logic and Applications, 2009. FPL 2009 2009, 174-179.
Duller A, Panesar G, Towner D: Parallel processing--the picoChip way! Commun Process Archit 2003, 125-138.
Agarwal A: The Tile Processor: A 64-core Multicore for Embedded Processing. Proceedings of HPEC Workshop 2007.
Hannig F, Ruckdeschel H, Dutta H, Teich J: Paro: Synthesis of hardware accelerators for multi-dimensional dataflow-intensive applications. Reconfig Comput Archit Tools Appl 2008, 287-293.
Resco C, Nieto A, Osorio R, Brea V, Vilarino D: A Digital Cellular-Based System for Retinal Vessel-Tree Extraction. European Conference on Circuit Theory and Design, 2009. ECCTD 2009 2009, 835-838.
bf I Xilinx (Ed): Virtex-6 Family Overview In DS099 White Paper 2010.
Montes CA: Automatic Pixel-Parallel Extraction of the Retinal Vascular-Tree: Algorithm Design, On-Chip Implementation and Applications. PhD Thesis, Faculty of Informatics, University of A Coruna 2008.
Niemeijer M, Staal J, van Ginneken B, Loog M, Abramoff M: Comparative Study of Retinal Vessel Segmentation Methods on a New Publicly Available Database. Proceedings of SPIE 2004, 5370: 648.