Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture
Tóm tắt
Từ khóa
Tài liệu tham khảo
1) Alle, M., Varadarajan, K., Fell, A., Reddy C., R., Joseph, N., Das, S., Biswas, P., Chetia, J., Rao, A., Nandy, S.K. and Narayan, R.: REDEFINE: Runtime reconfigurable polymorphic ASIC, <i>ACM Trans. Embed. Comput. Syst.</i>, Vol.9, No.2, pp.1-48 (2009).
2) Alle, M., Varadarajan, K., Fell, A., Nandy, S.K. and Narayan, R.: Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures, <i>Proc. 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications</i>, Berlin, Heidelberg, pp.204-215, Springer-Verlag (2009).
3) Bobda, C.: <i>Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications</i>, Springer Publishing Company, Incorporated (2007).
5) Lattner, C. and Adve, V.: LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation, <i>CGO '04: Proc. International Symposium on Code Generation and Optimization</i>, Washington, DC, USA, p.75, IEEE Computer Society (2004).
6) DeHon, A. and Wawrzynek, J.: Reconfigurable computing: what, why, and implications for design automation, <i>DAC '99: Proc. 36th Annual ACM/IEEE Design Automation Conference</i>, New York, NY, USA, pp.610-615, ACM (1999).
7) Fell, A., Alle, M., Varadarajan, K., Biswas, P., Das, S., Chetia, J., Nandy, S.K. and Narayan, R.: Streaming FFT on REDEFINE-v2: An application-architecture design space exploration, <i>Proc. 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems</i>, <i>CASES '09</i>, New York, NY, USA, pp.127-136, ACM (2009).
8) Fell, A., Chetia, J., Biswas, P., Narayan, R. and Nandy, S.K.: Generic Routing Rules and a Scalable Access Enhancement for the Network-on-Chip RECONNECT, <i>IEEE International SOC Conference</i> (<i>SoCC</i>) (2009).
10) Girvan, M. and Newman, M.E.J.: Community structure in social and biological networks, <i>Proc. National Academy of Sciences of the United States of America</i>, Vol.99, No.12, pp.7821-7826 (2002).
11) Hartenstein, R.: A decade of reconfigurable computing: A visionary retrospective, <i>Proc. Design, Automation and Test in Europe</i> (<i>DATE</i>), pp.642-649 (2000).
12) Kernighan, B.W. and Lin, S.: An Efficient Heuristic Procedure for Partitioning Graphs, <i>The Bell System Technical Journal</i>, Vol.49, No.1, pp.291-307 (1970).
13) Krishnamoorthy, R., Varadarajan, K., Garga, G., Alle, M., Nandy, S.K., Narayan, R. and Fujita, M.: Towards Minimizing Execution Delays on Dynamically Reconfigurable Processors: A case study on REDEFINE, <i>Proc. 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems</i>, <i>CASES '10</i>, New York, NY, USA, ACM (2010).
15) Mahlke, S.A., Lin, D.C., Chen, W.Y., Hank, R.E. and Bringmann, R.A.: Effective Compiler Support for Predicated Execution Using the Hyperblock, <i>MICRO 25: Proc. 25th Annual International Symposium on Microarchitecture</i>, Portland, Oregon, pp.45-54, IEEE Computer Society TC-MICRO and ACM SIGMICRO (1992).
16) Pandey, A. and Vemuri, R.: Combined Temporal Partitioning and Scheduling for Reconfigurable Architectures, <i>SPIE Conference on Configurable Computing: Technology and Applications</i> (1999).
17) Paulin, P.G. and Knight, J.P.: Force-directed scheduling in automatic data path synthesis, <i>DAC '87: Proc. 24th ACM/IEEE Design Automation Conference</i>, New York, NY, USA, pp.195-202, ACM (1987).
18) Paulin, P.G. and Knight, J.P.: Scheduling and binding algorithms for high-level synthesis, <i>DAC '89: Proc. 26th ACM/IEEE Design Automation Conference</i>, New York, NY, USA, pp.1-6, ACM (1989).
19) Sankaralingam, K., Nagarajan, R., Liu, H., Kim, C., Huh, J., Burger, D., Keckler, S.W. and Moore, C.R.: Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture, <i>Proc. 30th Ann. Intl Symp. on Computer Architecture</i> (<i>30th ISCA 2003</i>), <i>FCRC'03, ACM Computer Architecture News</i> (<i>CAN</i>), San Diego, CA, pp.422-432, ACM SIGARCH/IEEE CS (2003). Published as <i>Proc. 30th Ann. Intl Symp. on Computer Architecture</i> (<i>30th ISCA 2003</i>), <i>FCRC'03</i>, <i>ACM Computer Architecture News</i> (<i>CAN</i>), Vol.31, No.2, UT Austin.
20) Swanson, S., Schwerin, A., Mercaldi, M., Petersen, A., Putnam, A., Michelson, K., Oskin, M. and Eggers, S.J.: The WaveScalar architecture, <i>ACM Trans. Comput. Syst.</i>, Vol.25, No.2, pp.1-54 (2007).
21) Taylor, M.B., Lee, J.-w., Seneski, M. and Frank, M.: The RAW Microprocessor: A Computational Fabric for Software Circuits and General-Purpose programs Microprocessor, <i>Ieee Micro</i>, pp.25-35 (2002).
22) Trimberger, S.: Scheduling designs into a time-multiplexed FPGA, <i>FPGA '98: Proc. 1998 ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays</i>, New York, NY, USA, pp.153-160, ACM (1998).
23) Yang, H. and Wong, D.F.: Efficient network flow based min-cut balanced partitioning, <i>ICCAD '94: Proc. 1994 IEEE/ACM International Conference on Computer-aided design</i>, Los Alamitos, CA, USA, pp.50-55, IEEE Computer Society Press (1994).
