Performance computation for precharacterized CMOS gates with RC loads

Florentin Dartu1, N. Menezes2, Lawrence T. Pileggi3
1Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
2Intel Corporation, Hillsboro, OR, USA
3Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA

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10.1109/43.45867

10.1109/TCAD.1987.1270311

10.1109/TCAD.1985.1270130

dartu, 1994, a gate-delay model for high-speed cmos circuits, 31st Design Automation Conference, 576, 10.1145/196244.196562

dartu, 1994, a gate-delay model for high-speed cmos circuits, 31st Design Automation Conference, 576, 10.1145/196244.196562

10.1109/43.285250

10.1109/43.331409

10.1109/CICC.1992.591314

10.1109/JSSC.1984.1052168

10.1109/ICCD.1994.331929

george, 1994, power analysis and characterization for semi-custom design, Proc Int Workshop Low Power Design, 215

10.1109/4.126534

o brien, 1989, modeling the driving-point characteristic of resistive interconnect for accurate delay estimation, Proc IEEE Int Conf Computer&#x2010 Aided Design, 512

weste, 1992, principles of cmos vlsi design, Empirical Delay Models, 213

10.1109/ICCAD.1991.185195