[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"_public_publisher_byId_d20e3c75-c0e3-43e6-8005-9f3a11e4a854":3,"_public_publication_all{\"sortAscending\":false,\"sortField\":\"updateTime\",\"page\":0,\"size\":10,\"facet\":true,\"searchKey\":\"publisherId:d20e3c75-c0e3-43e6-8005-9f3a11e4a854,\"}":169},{"code":4,"data":5,"meta":20},"SUCCESS",{"id":6,"createTime":7,"updateTime":8,"relativeEntities":9,"slug":10,"properties":11,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":22,"manageAffiliations":29,"indexDatabases":45,"url":20,"thumbnailPath":20,"statistic":80,"gsStatistic":20,"type":20,"analyzePriority":20},"d20e3c75-c0e3-43e6-8005-9f3a11e4a854","2024-04-18T00:37:56.098+00:00","2025-11-21T10:02:18.179+00:00",[],"Springer-Science-and-Business-Media-LLC",{"issn":12,"title":14,"eissn":16},{"VOID":13},"0923-8174",{"EN":15},"Springer Science and Business Media LLC",{"VOID":17},"1573-0727","PUBLISHER","PENDING",null,0,[23],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":25,"label":26,"description":28,"parentId":20,"standard":20,"scholarHubFieldId":20},"3ca6493e-aecd-4733-965c-52fbf88fe329",[],{"EN":27},"Electrical and Electronic Engineering",{},[30,38],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":32,"slug":20,"properties":33,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":36,"statistic":20},"b2bfac93-563a-4fa4-bd81-e546a66bf9bd",[],{"title":34},{"EN":35},"Springer Netherlands",[37],"9a7c7208-b28a-42c2-a634-5a7f90eee3ab",{"id":39,"createTime":20,"updateTime":20,"relativeEntities":40,"slug":20,"properties":41,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":44,"statistic":20},"26a19206-5cad-4456-bb2f-49abd254fbc6",[],{"title":42},{"EN":43},"SPRINGER",[],[46,63],{"id":47,"indexDatabase":48,"url":58,"indexYears":59,"academicFieldIds":60,"indexDatabaseRanking":62},"96e2d701-6923-40c9-9a78-02b99a207bd7",{"id":49,"createTime":20,"updateTime":20,"relativeEntities":50,"label":51,"description":53,"key":55,"publicationTags":56,"standard":20},"3c7051d4-eb7d-4c57-a56b-36fc74c5d1e9",[],{"EN":52,"VI":52},"Scopus - Elsevier",{"EN":52,"VI":54},"Cơ sở dữ liệu Scopus thuộc Elsevier","scopus",[57],"SCOPUS","https:\u002F\u002Fwww.scopus.com\u002Fsourceid\u002F18040","1990-2025",[61],"a81768cc-7885-48eb-a85a-170d5a0a5f4f","SCOPUS__Q3",{"id":64,"indexDatabase":65,"url":77,"indexYears":20,"academicFieldIds":78,"indexDatabaseRanking":20},"baee5250-3d98-4956-a055-5ac241d084ff",{"id":66,"createTime":20,"updateTime":20,"relativeEntities":67,"label":68,"description":70,"key":73,"publicationTags":74,"standard":20},"a4921856-b128-4d9f-8f1f-e80813d3bbd4",[],{"EN":69,"VI":69},"ISI\u002FSCIE - Science Citation Index Expanded",{"EN":71,"VI":72},"SCIE database","Cơ sở dữ liệu SCIE","scie",[75,76],"SCIE","ISI","https:\u002F\u002Fmjl.clarivate.com\u002Fsearch-results?issn=0923-8174",[79],"751df115-4b08-418e-b118-c9d9a4c8e64c",{"impactFactor":21,"impactFactorByYear":81,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":93,"totalCitation":117,"totalCitationByYear":118,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":141,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},0.13,0.14,0.23,0.31,0.1,0.07,0.17,0.22,46,1,1494,{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},23,30,26,31,40,34,43,44,33,41,37,53,49,50,28,48,58,65,36,54,52,42,17,1520,{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},11,88,27,72,62,125,63,147,120,70,90,102,101,9,91,32,38,24,19,4,2,1.02,{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},1.22,0.37,3.38,1.16,1.27,0.68,2.12,2.5,1.91,2.77,2.45,1.64,1.46,0.8,1.55,1.57,2.02,0.25,0.74,1.72,0.62,0.83,0.48,0.39,0.08,0.05,18,{"meta":170,"data":172},{"total":171},"1352",[173,300,403,494,582,775,871,1062,1336,1519],{"id":174,"createTime":175,"updateTime":176,"relativeEntities":177,"slug":178,"properties":179,"entityType":190,"verifyStatus":191,"verifyTime":192,"verifyNote":193,"languages":20,"translateLanguages":20,"viewCount":91,"primaryUrl":194,"fullTextUrl":20,"authors":195,"publicationType":244,"publisherRelationship":245,"citationCount":21,"citationInfo":293,"publishDate":296,"publishYear":294,"citationAnalyzeStatus":19,"lastCitationAnalyze":297,"indexDatabases":298,"openAccess":20,"references":20,"isForceReanalyzing":299},"5620b846-14c3-45ed-8114-fbfdf57c0c98","2024-02-16T21:50:24.102+00:00","2026-07-22T17:42:26.633+00:00",[],"Soft-Errors-Sensitivity-of-SRAM-Cells-in-Hold-Write-Read-and-Half-Selected-Conditions",{"abstract":180,"title":182,"gsPaper":184,"references":186,"doi":188},{"EN":181},"This work evaluates the Soft Error sensitivity of the complete SRAM architecture using the 16 nm Bulk CMOS technology model. The paper investigated the fault propagation in cells and bitlines during the Hold, Read, Write operations, and the half-selection situation. The 6T, 8T, 9T, 8TSER, and DICE SRAM cells are compared not only about the radiation effects but also observing the timing, power, and static noise margin outcomes. DICE cell presents the highest robustness to the radiation effects. The 8T-SER presented the best stability results. The half-selection situation shows the potential to increase the cell sensitivity by  \n                \n                  \n                \n                $$\\approx$$\n                \n               50 \n                \n                  \n                \n                $$\\%$$\n                \n               compared to the Hold perspective.",{"EN":183},"Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions",{"VOID":185},"[\"7036809794160997277\"]",{"VOID":187},"Alorda B, Torrens G, Bota S, Segura J (2011) 8T vs. 6T SRAM cell radiation robustness: A comparative analysis. Proc Microelectron Reliab. 51(2):350–359. https:\u002F\u002Fdoi.org\u002F10.1016\u002Fj.microrel.2010.09.002\nArtola L, Hubert G, Alioto M (2014) Comparative soft error evaluation of layout cells in finFET technology. Proc Microelectron Reliab 54(9–10):2300–2305. https:\u002F\u002Fdoi.org\u002F10.1016\u002Fj.microrel.2014.07.109\nAsai S (2019) VLSI Design and Test for Systems Dependability. Springer. https:\u002F\u002Fdoi.org\u002F10.1007\u002F978-4-431-56594-9\nASU. Predictive technology model. Accessible in: http:\u002F\u002Fptm.asu.edu, last access: 5 Nov 2019\nCalin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. Proc IEEE Trans Nucl Sci 43(6):2874–2878. https:\u002F\u002Fdoi.org\u002F10.1109\u002F23.556880\nDodd PE, Massengill LW (2003) Basic mechanisms and modeling of single-event upset in digital microelectronics. Proc IEEE Trans Nucl Sci 50(3):583–602. https:\u002F\u002Fdoi.org\u002F10.1109\u002FTNS.2003.813129\nHubert G, Artola L, Regis D (2015) Impact of scaling on the soft error sensitivity of bulk, FDSOI and finFET technologies due to atmospheric radiation. Proc Integration 50:39–47. https:\u002F\u002Fdoi.org\u002F10.1016\u002Fj.vlsi.2015.01.003\nKim TT, Lee ZC, Do AT (2018) A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation. Proc Solid State Electron 139:60–68. https:\u002F\u002Fdoi.org\u002F10.1016\u002Fj.sse.2017.10.002\nManabe S, Watanabe Y, Liao W, Hashimoto M, Abe S-I (2019) Estimation of muon-induced SEU rates for 65-nm bulk and UTBB-SOI SRAMs. Proc IEEE Trans Nucl Sci. 66(7):1398-1403 https:\u002F\u002Fdoi.org\u002F10.1109\u002FTNS.2019.2916191\nMarques CM, Meinhardt C, Butzen PF (2020) Soft error reliability of SRAM cells during the three operation states. Proc IEEE Latin-American Test Symposium, p 1–6. https:\u002F\u002Fdoi.org\u002F10.1109\u002FLATS49555.2020.9093684\nMessenger GC (1982) Collection of charge on junction nodes from ion tracks. Proc IEEE Trans Nucl Sci 29(6):2024–2031. https:\u002F\u002Fdoi.org\u002F10.1109\u002FTNS.1982.4336490\nNGSPICE. Open source spice simulator. Accessible in: http:\u002F\u002Fngspice.sourceforge.net\u002Findex.html., last access: 5 Nov 2019\nNicolaidis M (2005) Design for soft error mitigation. Proc IEEE Trans Device Mater Reliab 5(3):405–418. https:\u002F\u002Fdoi.org\u002F10.1109\u002FTDMR.2005.855790\nNoh J et al (2015) Study of neutron soft error rate (SER) sensitivity: Investigation of upset mechanisms by comparative simulation of finFET and planar MOSFET SRAMs. Proc IEEE Trans Nucl Sci 62(4):1642–1649. https:\u002F\u002Fdoi.org\u002F10.1109\u002FTNS.2015.2450997\nPavlov A, Sachdev M (2008) CMOS SRAM circuit design and parametric test in nano-scaled technologies: process-aware SRAM design and test, volume 40. Springer Science & Business Media: ISBN 978-1-4020-8363-1\nRajendran A, Shiyanovskii Y, Wolff F, Papachristou C (2011) Noise margin, critical charge and power-delay tradeoffs for SRAM design. Proc IEEE Int On-Line Testing Symposium, p 145–150. https:\u002F\u002Fdoi.org\u002F10.1109\u002FIOLTS.2011.5993828\nRajput AS, Pattanaik M, Tiwari RK (2018) Estimation of static noise margin by butterfly method using curve-fitting technique. Journal of Active and Passive Electronic Devices 13(1):1–9\nSajit AS, Turi MA (2017) SEU tolerance of finFET 6T SRAM, 8T SRAM and DICE memory cells. In Proc IEEE Computing and Communication Workshop and Conference (CCWC), p 1–5. IEEE. https:\u002F\u002Fdoi.org\u002F10.1109\u002FCCWC.2017.7868477\nSamandari-Rad J, Hughey R (2016) Power\u002Fenergy minimization techniques for variability-aware high-performance 16-nm 6t-SRAM. Proc IEEE Access 4:594–613. https:\u002F\u002Fdoi.org\u002F10.1109\u002FACCESS.2016.2521385\nSeevinck E, List FJ, Lohstroh J (1987) Static-noise margin analysis of MOS SRAM cells. Proc IEEE J. Solid State Circuits 22(5):748–754. https:\u002F\u002Fdoi.org\u002F10.1109\u002FJSSC.1987.1052809\nShah JS, Nairn D, Sachdev M (2015) A 32 kb macro with 8T soft error robust, SRAM cell in 65-nm CMOS. Proc IEEE Trans Nucl Sci 62(3):1367-1374. https:\u002F\u002Fdoi.org\u002F10.1109\u002FTNS.2015.2429589\nUznanski S, Gasiot G, Roche P, Tavernier C, Autran J-L (2010) Single event upset and multiple cell upset modeling in commercial bulk 65-nm CMOS SRAMs and flip-flops. Proc IEEE Trans Nucl Sci 57(4):1876–1883. https:\u002F\u002Fdoi.org\u002F10.1109\u002FTNS.2010.2051039\nVargas F, Nicolaidis M (1994) SEU-tolerant SRAM design based on current monitoring. In Proc IEEE Int Symposium on Fault-Tolerant Computing, p 106–115. IEEE. https:\u002F\u002Fdoi.org\u002F10.1109\u002FFTCS.1994.315652",{"VOID":189},"10.1007\u002Fs10836-021-05944-2","PUBLICATION","VERIFIED","2024-06-24T01:59:47.966+00:00","Auto Verify","https:\u002F\u002Flink.springer.com\u002Farticle\u002F10.1007\u002Fs10836-021-05944-2",[196,212,229],{"id":197,"sortIndex":21,"researcher":20,"roles":198,"affiliations":200,"properties":209,"displayName":211,"givenName":20,"familyName":20},"ae2f9039-c669-4de3-ac3c-889cee3c72a4",[199],"AUTHOR",[201],{"id":202,"sortIndex":21,"affiliation":203,"properties":20},"af788015-cb09-4820-b710-65e123b315f8",{"id":202,"createTime":20,"updateTime":20,"relativeEntities":204,"slug":20,"properties":205,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":208,"statistic":20},[],{"title":206},{"VI":207},"Universidade Federal do Rio Grande do Sul - UFRGS, PGMICRO, Porto Alegre, Brazil",[],{"title":210},{"VI":211},"Cleiton Magano Marques",{"id":213,"sortIndex":91,"researcher":20,"roles":214,"affiliations":215,"properties":224,"displayName":226,"givenName":20,"familyName":20},"ac9cc6a6-df4d-4a73-b867-12f109c02fca",[199],[216],{"id":217,"sortIndex":21,"affiliation":218,"properties":20},"55b95070-3a6a-42de-8671-05dda1b0f9da",{"id":217,"createTime":20,"updateTime":20,"relativeEntities":219,"slug":20,"properties":220,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":223,"statistic":20},[],{"title":221},{"VI":222},"Universidade Federal de Santa Catarina - UFSC, PPGCC, Florianópolis, Brazil",[],{"title":225,"gsAuthor":227},{"VI":226},"Cristina Meinhardt",{"VOID":228},"[\"nSxMVPkAAAAJ\"]",{"id":230,"sortIndex":139,"researcher":20,"roles":231,"affiliations":232,"properties":239,"displayName":241,"givenName":20,"familyName":20},"0e7795ae-41a0-4440-ac31-13ab71f215bb",[199],[233],{"id":202,"sortIndex":21,"affiliation":234,"properties":20},{"id":202,"createTime":20,"updateTime":20,"relativeEntities":235,"slug":20,"properties":236,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":238,"statistic":20},[],{"title":237},{"VI":207},[],{"title":240,"gsAuthor":242},{"VI":241},"Paulo Francisco Butzen",{"VOID":243},"[\"2VeTdosAAAAJ\"]","ARTICLE",{"url":194,"publisher":246,"properties":288},{"id":6,"createTime":7,"updateTime":8,"relativeEntities":247,"slug":10,"properties":248,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":252,"manageAffiliations":257,"indexDatabases":268,"url":20,"thumbnailPath":20,"statistic":283,"gsStatistic":20,"type":20,"analyzePriority":20},[],{"issn":249,"title":250,"eissn":251},{"VOID":13},{"EN":15},{"VOID":17},[253],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":254,"label":255,"description":256,"parentId":20,"standard":20,"scholarHubFieldId":20},[],{"EN":27},{},[258,263],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":259,"slug":20,"properties":260,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":262,"statistic":20},[],{"title":261},{"EN":35},[37],{"id":39,"createTime":20,"updateTime":20,"relativeEntities":264,"slug":20,"properties":265,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":267,"statistic":20},[],{"title":266},{"EN":43},[],[269,276],{"id":47,"indexDatabase":270,"url":58,"indexYears":59,"academicFieldIds":275,"indexDatabaseRanking":62},{"id":49,"createTime":20,"updateTime":20,"relativeEntities":271,"label":272,"description":273,"key":55,"publicationTags":274,"standard":20},[],{"EN":52,"VI":52},{"EN":52,"VI":54},[57],[61],{"id":64,"indexDatabase":277,"url":77,"indexYears":20,"academicFieldIds":282,"indexDatabaseRanking":20},{"id":66,"createTime":20,"updateTime":20,"relativeEntities":278,"label":279,"description":280,"key":73,"publicationTags":281,"standard":20},[],{"EN":69,"VI":69},{"EN":71,"VI":72},[75,76],[79],{"impactFactor":21,"impactFactorByYear":284,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":285,"totalCitation":117,"totalCitationByYear":286,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":287,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},{"pages":289,"volume":291},{"VOID":290},"263-270",{"VOID":292},"37",{"total":21,"publishYear":294,"statisticByYear":295},2021,{},"2021-05-06","2026-07-22T17:42:26.632+00:00",[62,75],false,{"id":301,"createTime":302,"updateTime":303,"relativeEntities":304,"slug":305,"properties":306,"entityType":190,"verifyStatus":191,"verifyTime":317,"verifyNote":193,"languages":20,"translateLanguages":20,"viewCount":21,"primaryUrl":318,"fullTextUrl":20,"authors":319,"publicationType":244,"publisherRelationship":350,"citationCount":20,"citationInfo":20,"publishDate":398,"publishYear":399,"citationAnalyzeStatus":400,"lastCitationAnalyze":401,"indexDatabases":402,"openAccess":20,"references":20,"isForceReanalyzing":299},"9e9c9ff6-8a94-42eb-8163-7212162d7f75","2023-12-23T07:28:29.816+00:00","2026-07-22T02:02:17.435+00:00",[],"A-test-methodology-for-finite-state-machines-using-partial-scan-design",{"abstract":307,"title":309,"gsPaper":311,"references":313,"doi":315},{"EN":308},"This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.",{"EN":310},"A test methodology for finite state machines using partial scan design",{"VOID":312},"[]",{"VOID":314},"R.A. Marlett, “EBT: A comprehensive test generation technique for highly sequential circuits,” Proceedings of the 15th Design Automation Conference, pp. 335–339, June 1978.\nR.A. Marlett, “An effective test generation system for sequential circuits,” Proceedings of the 23rd Design Automation Conference, pp. 250–256, June 1986.\nH.K.T. Ma, S. Devadas, A.R. Newton, and A. SangiovanniVincentelli, “Test generation for sequential finite state machines,” Proceedings of the International Conference on Computer Aided Design, pp. 288–291, Nov. 1987.\nW.T. Cheng, “The back algorithm for sequential test generation,” Proceedings of the International Conference on Computer Design, pp. 66–69, October 1988.\nM.H. Schulz, and E. Auth, “ESSENTIAL: An efficient selflearning test pattern generation algorithm for sequential circuits,” Proceedings of the International Test Conference, pp. 28–37, August 1989.\nE.B. Eichelberger, and T.W. Williams, “A logic design structure of LSI testing,” Proceedings of the 14th Design Automation Conference, pp. 462–468, June 1977.\nE. Trischler, “Testability Analysis and Incomplete Scan Path,” Proceedings of International Conference on Computer Aided Design, pp. 38–39, Oct. 1983.\nV.D. Agrawal, K.T. Cheng, D.D. Johnson, and T. Lin, “A complete solution to the partial scan problem,” Proceedings of the International Test Conference, pp. 44–51, 1987.\nK.T. Cheng, and V.D. Agrawal, “A partial scan method for sequential circuits with feedback,” IEEE Transactions on Computers, vol. C-39, pp. 544–548, April 1990.\nS. Lee, and K.G. Shin, “Design for test using partial parallel scan,” IEEE Transactions on Computer-Aided design, vol. CAD-9, pp. 203–211, February 1990.\nR. Gupta, R. Gupta, and M.A. Breuer, “The BALLAST methodology for structured partial scan design,” IEEE Transactions on Computers, vol. C-39, pp. 538–544, April 1990.\nA. Miczo, Digital Logic Testing and Simulation, New York: Harper & Row, pp. 98–103, 1986.\nF. Brglez, D. Bryan, and C. Kozminski, “Combinational profiles of sequential benchmark circuits,” special session on benchmarks for sequential test pattern generation, Proceedings of the International Symposium on Circuits and Systems, 1989.\nP. Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits,” IEEE Transactions on Computers, vol. C-30, pp. 215–222, March 1981.\nH. Fujiwara, and T. Shimono, “On the acceleration of test generation algorithms,” IEEE Transactions on Computers, vol. C-32, pp. 1137–1144, December 1983.\nM.H. Schulz, E. Trischler, and T.M. Sarfert, “SOCRATES: A highly efficient automatic test pattern generation system,” IEEE Transactions on Computer-Aided Design, vol. CAD-7, pp. 126–137, January 1988.\nK.T. Cheng, and V.D. Agrawal, “An economical scan design for sequential logic test generation,” Proceedings of the 19th Symposium on Fault Tolerant Computing, pp. 28–35, June 1989.\nE. Horowitz, and S. Sahni, Fundamentals of Computer Algorithms, Potomac, MD: Computer Science Press, p. 193, 1978.\nP. Goel, “Test generation costs analysis and projections,” Proceedings of the 17th ACM\u002FIEEE Design Automation Conference, pp. 77–84, June 1980.\nH.B. Min, and W.A. Rogers, “Search strategy switching: An alternative to increased backtracking,” Proceedings of the International Test Conference, pp. 803–811, August 1989.\nR. Tarjan, “Finding dominators in directed graph,” SIAM Journal on Computing, vol. 3, pp. 62–89, 1974.\nD.B. Johnson, “Finding all the elementary circuits of a directed graph,” SIAM Journal on Computing, vol. 4, (1), pp. 77–84, 1975.",{"VOID":316},"10.1007\u002FBF00137250","2024-06-26T21:26:47.286+00:00","https:\u002F\u002Flink.springer.com\u002Farticle\u002F10.1007\u002FBF00137250",[320,335],{"id":321,"sortIndex":21,"researcher":20,"roles":322,"affiliations":323,"properties":332,"displayName":334,"givenName":20,"familyName":20},"18f16b09-5c1b-4502-9e30-ad775239cb1a",[199],[324],{"id":325,"sortIndex":21,"affiliation":326,"properties":20},"be681081-5372-4668-977d-94f6ba44202b",{"id":325,"createTime":20,"updateTime":20,"relativeEntities":327,"slug":20,"properties":328,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":331,"statistic":20},[],{"title":329},{"VI":330},"Department of Electrical and Computer Engineering, Su Win City, Korea",[],{"title":333},{"VI":334},"Hyoung B. Min",{"id":336,"sortIndex":91,"researcher":20,"roles":337,"affiliations":338,"properties":347,"displayName":349,"givenName":20,"familyName":20},"105837d6-5853-400b-925d-669a7114ed4a",[199],[339],{"id":340,"sortIndex":21,"affiliation":341,"properties":20},"4bfd4d07-3b19-4984-adfc-04483243dd08",{"id":340,"createTime":20,"updateTime":20,"relativeEntities":342,"slug":20,"properties":343,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":346,"statistic":20},[],{"title":344},{"VI":345},"Department of Electrical and Computer Engineering, Computer Enginering Research Center, University of Texas, Austin, USA",[],{"title":348},{"VI":349},"William A. Rogers",{"url":318,"publisher":351,"properties":393},{"id":6,"createTime":7,"updateTime":8,"relativeEntities":352,"slug":10,"properties":353,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":357,"manageAffiliations":362,"indexDatabases":373,"url":20,"thumbnailPath":20,"statistic":388,"gsStatistic":20,"type":20,"analyzePriority":20},[],{"issn":354,"title":355,"eissn":356},{"VOID":13},{"EN":15},{"VOID":17},[358],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":359,"label":360,"description":361,"parentId":20,"standard":20,"scholarHubFieldId":20},[],{"EN":27},{},[363,368],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":364,"slug":20,"properties":365,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":367,"statistic":20},[],{"title":366},{"EN":35},[37],{"id":39,"createTime":20,"updateTime":20,"relativeEntities":369,"slug":20,"properties":370,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":372,"statistic":20},[],{"title":371},{"EN":43},[],[374,381],{"id":47,"indexDatabase":375,"url":58,"indexYears":59,"academicFieldIds":380,"indexDatabaseRanking":62},{"id":49,"createTime":20,"updateTime":20,"relativeEntities":376,"label":377,"description":378,"key":55,"publicationTags":379,"standard":20},[],{"EN":52,"VI":52},{"EN":52,"VI":54},[57],[61],{"id":64,"indexDatabase":382,"url":77,"indexYears":20,"academicFieldIds":387,"indexDatabaseRanking":20},{"id":66,"createTime":20,"updateTime":20,"relativeEntities":383,"label":384,"description":385,"key":73,"publicationTags":386,"standard":20},[],{"EN":69,"VI":69},{"EN":71,"VI":72},[75,76],[79],{"impactFactor":21,"impactFactorByYear":389,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":390,"totalCitation":117,"totalCitationByYear":391,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":392,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},{"pages":394,"volume":396},{"VOID":395},"127-137",{"VOID":397},"3","1992-05-01",1992,"ERROR_IN_GET_PLATFORM_ID","2026-07-22T02:02:17.434+00:00",[62,75],{"id":404,"createTime":405,"updateTime":406,"relativeEntities":407,"slug":408,"properties":409,"entityType":190,"verifyStatus":191,"verifyTime":420,"verifyNote":193,"languages":20,"translateLanguages":20,"viewCount":21,"primaryUrl":421,"fullTextUrl":20,"authors":422,"publicationType":244,"publisherRelationship":438,"citationCount":486,"citationInfo":487,"publishDate":490,"publishYear":488,"citationAnalyzeStatus":491,"lastCitationAnalyze":492,"indexDatabases":493,"openAccess":20,"references":20,"isForceReanalyzing":299},"1ffaec6b-d4b7-4af0-812d-0cc7e528ecc4","2024-02-12T18:21:30.329+00:00","2026-07-21T18:12:30.894+00:00",[],"Yield-fluctuations-and-defect-models",{"abstract":410,"title":412,"gsPaper":414,"references":416,"doi":418},{"EN":411},"This paper establishes a general statistical framework for analyzing wafer fallout data in order to obtain information about process induced defects. The statistical behavior of fallout during testing is characterized. A general model is presented that relates the yield to the test coverage and the defect distribution. This model incorporates arbitrary variations in the occurrence probabilities of different defects and arbitrary dependencies between the defects, although it still ignores correlations between the occurrence probability of a defect and whether or not this defect is detected. A statistical acceptance criterion for this model is proposed, based on a convexity property of the model. It is applied to a published set of yield data and shows that some striking features in these data cannot be due to mere statistical fluctuations. Some explanations of these features will be discussed.",{"EN":413},"Yield fluctuations and defect models",{"VOID":415},"[\"11792372741754849127\"]",{"VOID":417},"P.C. Maxwell, R.C. Aitken, V. Johansen, and I. Chiang, “The Effect of Different Test sets on Quality Level Prediction: When is 80% Better than 90%?”Proceedings IEEE International Test Conference, October 1991, pp. 358–364.\nT.W. Williams and N. C. Brown, “Defect Level as a Function of Fault Coverage,”IEEE Transactions on Computers, Vol. C-30, pp. 987–988, December 1981.\nJ.E. Price, “A New Look at Yield of Integrated Circuits,”Proceedings of the IEEE, August 1970, Vol. 58, pp. 1290–1291.\nB.T. Murphy, “Comments on A New Look at Yield of Interated Circuits,”Proceedings of the IEEE, July 1971, Vol. 59, p. 1128.\nC.H. Stapper Jr., “On a Composite Model to theIC Yield Problem,”IEEE Journal of Solid-State Circuits, December 1975, pp. 537–539.\nC.H. Stapper Jr., “The Effects of Wafer to Wafer Defect Density Variations on Integrated Circuit Defect and Fault Distributions,”IBM Journal of Research and Development, January 1985, pp. 87–97.\nJ.A. Cunningham, “The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing.IEEE Transactions on Semiconductor Manufacturing, Vol. 3, pp. 60–71, May 1990.\nV.D. Agrawal, S.C. Seth, and P. Agrawal, “LSI Product Quality and Fault Coverage,”Proceedings IEEE 18th Design Automation Conference, 1981, pp. 196–203.\nS.C. Seth and V.D. Agrawal, “Characterizing the LSI Yield Equation from Wafer Test Data,”IEEE Transactions on Computer-Aided Design, Vol. CAD-3, pp. 123–126 April 1984.\nL.M. Huisman, “Fault Coverage and Yield Predictions: Do We Need more than 100% Coverage?”Proceedings IEEE European Test Conference, April 1993, pp. 180–187.\nD.V. Das, S.C. Seth, P.T. Wagner, J.C. Anderson, and V.D. Agrawal, “An Experimental Study on Reject Ratio Prediction for VLSI Circuits: Kokomo Revisited,”Proceedings IEEE International Test Conference, September 1990, pp. 712–720.\nP.C. Maxwell and R.C. Aitken, “Test Sets and Reject Rates: All Fault Coverages Are Not Created Equal,”IEEE Design & Test of Computers, March 1993, pp. 42–51.\nR.L. Wadsack, “VLSI: How much Fault Coverage is Enough?”Proceedings IEEE International Test Conference, 1981, pp. 547–554.\nW. Feller,An Introduction to Probability Theory and Its Applications, John Wiley & Sons, 1967.\nD. Das, S.C. Seth, and V.D. Agrawal, “Accurate Computation of Field Reject Ratio Based on Fault Latency,”IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 1, pp. 537–545, December 1993.\nV.D. Agrawal, S.C. Seth, and P. Agrawal, “Fault Coverage Requirements in Production Testing of LSI Circuits,IEEE Journal of Solid-State Circuits Vol. SC-17, pp. 57–61, 1982.\nT.W. Williams, “Test Length in a Self-Testing Environment,”IEEE Design & Test of Computers, Vol. 2, pp. 59–63, April 1985.\nC.H. Stapper,Correlation and Covariance in Integrated Circuit Yield Models, I.B.M., April 1986, TR 19.90250.\nE.J. Aas and V.T. Minh, “Detect Level Calculation: The Importance of Accurate Models for Defect Distribution and Multiple Fault Coverage in Low Yield Situations,”Proceedings ISCAS'89, 1989, pp. 939–944.\nB.W. Lindgren,Statistical Theory, MacMillan Publishing Col., Inc., 1976.\nM. Abramovici, M.A. Breuer, and A.D. Friedman,Digital Systems Testing and Testable Design, Computer Science Press, 1990.",{"VOID":419},"10.1007\u002FBF00995316","2024-05-28T01:57:22.161+00:00","https:\u002F\u002Flink.springer.com\u002Farticle\u002F10.1007\u002FBF00995316",[423],{"id":424,"sortIndex":21,"researcher":20,"roles":425,"affiliations":426,"properties":435,"displayName":437,"givenName":20,"familyName":20},"aa3652ad-b29b-4e30-b9ae-e4a26c20b954",[199],[427],{"id":428,"sortIndex":21,"affiliation":429,"properties":20},"9729a695-77e2-4c7f-80fb-6f35a1cf9887",{"id":428,"createTime":20,"updateTime":20,"relativeEntities":430,"slug":20,"properties":431,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":434,"statistic":20},[],{"title":432},{"VI":433},"IBM T. J. Watson Research Center, Yorktown Heights",[],{"title":436},{"VI":437},"Leendert M. Huisman",{"url":421,"publisher":439,"properties":481},{"id":6,"createTime":7,"updateTime":8,"relativeEntities":440,"slug":10,"properties":441,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":445,"manageAffiliations":450,"indexDatabases":461,"url":20,"thumbnailPath":20,"statistic":476,"gsStatistic":20,"type":20,"analyzePriority":20},[],{"issn":442,"title":443,"eissn":444},{"VOID":13},{"EN":15},{"VOID":17},[446],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":447,"label":448,"description":449,"parentId":20,"standard":20,"scholarHubFieldId":20},[],{"EN":27},{},[451,456],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":452,"slug":20,"properties":453,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":455,"statistic":20},[],{"title":454},{"EN":35},[37],{"id":39,"createTime":20,"updateTime":20,"relativeEntities":457,"slug":20,"properties":458,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":460,"statistic":20},[],{"title":459},{"EN":43},[],[462,469],{"id":47,"indexDatabase":463,"url":58,"indexYears":59,"academicFieldIds":468,"indexDatabaseRanking":62},{"id":49,"createTime":20,"updateTime":20,"relativeEntities":464,"label":465,"description":466,"key":55,"publicationTags":467,"standard":20},[],{"EN":52,"VI":52},{"EN":52,"VI":54},[57],[61],{"id":64,"indexDatabase":470,"url":77,"indexYears":20,"academicFieldIds":475,"indexDatabaseRanking":20},{"id":66,"createTime":20,"updateTime":20,"relativeEntities":471,"label":472,"description":473,"key":73,"publicationTags":474,"standard":20},[],{"EN":69,"VI":69},{"EN":71,"VI":72},[75,76],[79],{"impactFactor":21,"impactFactorByYear":477,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":478,"totalCitation":117,"totalCitationByYear":479,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":480,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},{"pages":482,"volume":484},{"VOID":483},"241-254",{"VOID":485},"7",3,{"total":486,"publishYear":488,"statisticByYear":489},1995,{},"1995-12-01","DONE_ANALYZE_CITATION","2026-07-21T18:12:30.893+00:00",[62,75],{"id":495,"createTime":496,"updateTime":497,"relativeEntities":498,"slug":499,"properties":500,"entityType":190,"verifyStatus":191,"verifyTime":511,"verifyNote":193,"languages":20,"translateLanguages":20,"viewCount":91,"primaryUrl":512,"fullTextUrl":20,"authors":513,"publicationType":244,"publisherRelationship":529,"citationCount":91,"citationInfo":577,"publishDate":579,"publishYear":488,"citationAnalyzeStatus":19,"lastCitationAnalyze":580,"indexDatabases":581,"openAccess":20,"references":20,"isForceReanalyzing":299},"c04bbff7-89fa-4712-809e-2dbaca4b428c","2024-01-29T15:28:26.488+00:00","2026-07-20T13:52:55.066+00:00",[],"Comments-on-Aliasing-Properties-of-Circular-MISRs-",{"abstract":501,"title":503,"gsPaper":505,"references":507,"doi":509},{"EN":502},"The analysis of aliasing probability presented in a recent article, “Aliasing Properties of Circular MISRs” [1], is based on an error model that cannot adequately represent real circuits. We show why conclusions presented in [1] should not be used in practice, substantiating our claim with experimental results.",{"EN":504},"Comments on “Aliasing Properties of Circular MISRs”",{"VOID":506},"[\"178541301811777341\"]",{"VOID":508},"G. Edirisooriya and J.P. Robinson, “Aliasing properties of circular misrs,”Journal of Electronic Testing: Theory and Applications, vol. 4, pp. 151–158, May 1993.\nF. Brglez and H. Fujiwara, “A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN,” Special Session on Recent Algorithms for Gate-Level ATPG with Fault Simulation and Their Performance Assessment,Proc. Int. Symp. Circuits and Systems, June 1985.\nW. Daehn, T.W. Williams, and K.D. Wagner, “Aliasing erross in linear automata used as multiple-input signature analyzers,”IBM Journal of Research and Development, vol. 34, pp. 363–380, March\u002FMay 1990.\nM. Damiani, P. Olivo, and B. Riccó, “Analysis and design of linear finite state machines for signature analysis testing,”IEEE Trans. Comput., vol. 40, pp. 1034–1045, September 1991.\nT. Kameda, S. Pilarski, and A. Ivanov, “Notes on multiple input signature analysis,”IEEE Trans. Comput., vol. 42, pp. 228–234, February 1993.\nS. Pilarski, T. Kameda, and A. Ivanov, “Sequential faults and aliasing,”IEEE Trans. CAD, vol. 12, pp. 1068–1074, July 1993.\nW.H. Debany, M.J. Gorniak, D.E. Daskiewich, A.R. Macera, K.A. Kwiat, and H.B. Dussault, “Empirical bounds on fault coverage loss due to LFSR aliasing,” inProc. IEEE VLSI Test Symposium, pp. 143–148, April 1992.",{"VOID":510},"10.1007\u002FBF00993137","2024-05-08T03:25:50.512+00:00","https:\u002F\u002Flink.springer.com\u002Farticle\u002F10.1007\u002FBF00993137",[514],{"id":515,"sortIndex":21,"researcher":20,"roles":516,"affiliations":517,"properties":526,"displayName":528,"givenName":20,"familyName":20},"4652f1db-0423-439a-bd35-814aac6f63e7",[199],[518],{"id":519,"sortIndex":21,"affiliation":520,"properties":20},"6507fd0b-70e9-4bd8-a86f-b6373e6c45af",{"id":519,"createTime":20,"updateTime":20,"relativeEntities":521,"slug":20,"properties":522,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":525,"statistic":20},[],{"title":523},{"VI":524},"School of Computing Science, Simon Fraser University, Burnaby, Canada",[],{"title":527},{"VI":528},"Slawomir Pilarski",{"url":512,"publisher":530,"properties":572},{"id":6,"createTime":7,"updateTime":8,"relativeEntities":531,"slug":10,"properties":532,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":536,"manageAffiliations":541,"indexDatabases":552,"url":20,"thumbnailPath":20,"statistic":567,"gsStatistic":20,"type":20,"analyzePriority":20},[],{"issn":533,"title":534,"eissn":535},{"VOID":13},{"EN":15},{"VOID":17},[537],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":538,"label":539,"description":540,"parentId":20,"standard":20,"scholarHubFieldId":20},[],{"EN":27},{},[542,547],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":543,"slug":20,"properties":544,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":546,"statistic":20},[],{"title":545},{"EN":35},[37],{"id":39,"createTime":20,"updateTime":20,"relativeEntities":548,"slug":20,"properties":549,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":551,"statistic":20},[],{"title":550},{"EN":43},[],[553,560],{"id":47,"indexDatabase":554,"url":58,"indexYears":59,"academicFieldIds":559,"indexDatabaseRanking":62},{"id":49,"createTime":20,"updateTime":20,"relativeEntities":555,"label":556,"description":557,"key":55,"publicationTags":558,"standard":20},[],{"EN":52,"VI":52},{"EN":52,"VI":54},[57],[61],{"id":64,"indexDatabase":561,"url":77,"indexYears":20,"academicFieldIds":566,"indexDatabaseRanking":20},{"id":66,"createTime":20,"updateTime":20,"relativeEntities":562,"label":563,"description":564,"key":73,"publicationTags":565,"standard":20},[],{"EN":69,"VI":69},{"EN":71,"VI":72},[75,76],[79],{"impactFactor":21,"impactFactorByYear":568,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":569,"totalCitation":117,"totalCitationByYear":570,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":571,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},{"pages":573,"volume":575},{"VOID":574},"139-140",{"VOID":576},"6",{"total":91,"publishYear":488,"statisticByYear":578},{"1999":91},"1995-02-01","2026-07-20T13:52:55.065+00:00",[62,75],{"id":583,"createTime":584,"updateTime":585,"relativeEntities":586,"slug":587,"properties":588,"entityType":190,"verifyStatus":191,"verifyTime":597,"verifyNote":193,"languages":20,"translateLanguages":20,"viewCount":21,"primaryUrl":598,"fullTextUrl":20,"authors":599,"publicationType":244,"publisherRelationship":656,"citationCount":21,"citationInfo":704,"publishDate":707,"publishYear":705,"citationAnalyzeStatus":19,"lastCitationAnalyze":708,"indexDatabases":709,"openAccess":20,"references":710,"isForceReanalyzing":299},"481ad798-c8c6-44d6-8049-0d9c0c51d0f9","2024-02-09T06:44:18.557+00:00","2026-07-17T13:10:56.805+00:00",[],"A-Low-Power-Online-Test-Method-for-FPGA-Single-Solder-Joint-Resistance",{"abstract":589,"title":591,"gsPaper":593,"doi":595},{"EN":590},"Solder joint resistance monitoring is important for electronic system prognostics and system health management. It is noted that the typical built-in self-test method of FPGA solder joint has shortcomings of large power consumption, unavailability of test pins in FPGA’s functional design and possible difficulty in location arrangement of solder joint when two pins need to be measured simultaneously. To overcome these drawbacks, an online measuring method for single solder joint resistance with the constraints of limited pin number and low power consumption is proposed. The test model of the method is introduced in detail and the power consumption is theoretically analyzed. Furthermore, corresponding experimental platform is built based on a Spartan 6 FPGA and experiments are conducted. The test results show that the method can be used for online measurement of a solder joint’s resistance of an output pin in an FPGA design with very low power consumption.",{"EN":592},"A Low Power Online Test Method for FPGA Single Solder Joint Resistance",{"VOID":594},"[\"16740110218349611767\"]",{"VOID":596},"10.1007\u002Fs10836-017-5698-1","2024-04-30T15:56:21.983+00:00","https:\u002F\u002Flink.springer.com\u002Farticle\u002F10.1007\u002Fs10836-017-5698-1",[600,615,628,641],{"id":601,"sortIndex":21,"researcher":20,"roles":602,"affiliations":603,"properties":612,"displayName":614,"givenName":20,"familyName":20},"3869c897-3b85-489a-aa66-82ca3dbb40e5",[199],[604],{"id":605,"sortIndex":21,"affiliation":606,"properties":20},"918a3bd6-dd74-4d67-a837-bc19d0232007",{"id":605,"createTime":20,"updateTime":20,"relativeEntities":607,"slug":20,"properties":608,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":611,"statistic":20},[],{"title":609},{"VI":610},"Hypervelocity Aerodynamics Institute, China Aerodynamics Research and Development Center, Mianyang, China",[],{"title":613},{"VI":614},"Nantian Wang",{"id":616,"sortIndex":91,"researcher":20,"roles":617,"affiliations":618,"properties":625,"displayName":627,"givenName":20,"familyName":20},"30f093e3-363a-4aba-9a1e-1ba81e678f6c",[199],[619],{"id":605,"sortIndex":21,"affiliation":620,"properties":20},{"id":605,"createTime":20,"updateTime":20,"relativeEntities":621,"slug":20,"properties":622,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":624,"statistic":20},[],{"title":623},{"VI":610},[],{"title":626},{"VI":627},"Xiaoyu Ma",{"id":629,"sortIndex":139,"researcher":20,"roles":630,"affiliations":631,"properties":638,"displayName":640,"givenName":20,"familyName":20},"7296d413-13b2-4489-a8ce-af77be531787",[199],[632],{"id":605,"sortIndex":21,"affiliation":633,"properties":20},{"id":605,"createTime":20,"updateTime":20,"relativeEntities":634,"slug":20,"properties":635,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":637,"statistic":20},[],{"title":636},{"VI":610},[],{"title":639},{"VI":640},"Xiaobin Xu",{"id":642,"sortIndex":486,"researcher":20,"roles":643,"affiliations":644,"properties":653,"displayName":655,"givenName":20,"familyName":20},"01ad3899-deb7-4f6f-816d-2c455e833603",[199],[645],{"id":646,"sortIndex":21,"affiliation":647,"properties":20},"3011c782-e2c5-4ed4-b06f-218e922dab89",{"id":646,"createTime":20,"updateTime":20,"relativeEntities":648,"slug":20,"properties":649,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":652,"statistic":20},[],{"title":650},{"VI":651},"Chongqing Communication College, Chongqing, China",[],{"title":654},{"VI":655},"Ziqiao Rui",{"url":598,"publisher":657,"properties":699},{"id":6,"createTime":7,"updateTime":8,"relativeEntities":658,"slug":10,"properties":659,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":663,"manageAffiliations":668,"indexDatabases":679,"url":20,"thumbnailPath":20,"statistic":694,"gsStatistic":20,"type":20,"analyzePriority":20},[],{"issn":660,"title":661,"eissn":662},{"VOID":13},{"EN":15},{"VOID":17},[664],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":665,"label":666,"description":667,"parentId":20,"standard":20,"scholarHubFieldId":20},[],{"EN":27},{},[669,674],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":670,"slug":20,"properties":671,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":673,"statistic":20},[],{"title":672},{"EN":35},[37],{"id":39,"createTime":20,"updateTime":20,"relativeEntities":675,"slug":20,"properties":676,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":678,"statistic":20},[],{"title":677},{"EN":43},[],[680,687],{"id":47,"indexDatabase":681,"url":58,"indexYears":59,"academicFieldIds":686,"indexDatabaseRanking":62},{"id":49,"createTime":20,"updateTime":20,"relativeEntities":682,"label":683,"description":684,"key":55,"publicationTags":685,"standard":20},[],{"EN":52,"VI":52},{"EN":52,"VI":54},[57],[61],{"id":64,"indexDatabase":688,"url":77,"indexYears":20,"academicFieldIds":693,"indexDatabaseRanking":20},{"id":66,"createTime":20,"updateTime":20,"relativeEntities":689,"label":690,"description":691,"key":73,"publicationTags":692,"standard":20},[],{"EN":69,"VI":69},{"EN":71,"VI":72},[75,76],[79],{"impactFactor":21,"impactFactorByYear":695,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":696,"totalCitation":117,"totalCitationByYear":697,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":698,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},{"pages":700,"volume":702},{"VOID":701},"775-780",{"VOID":703},"33",{"total":21,"publishYear":705,"statisticByYear":706},2017,{},"2017-12-11","2026-07-17T13:10:56.804+00:00",[62,75],[711,717,720,723,727,730,733,736,739,742,748,751,754,760,763,766,769],{"id":712,"text":713,"url":714,"identifiers":715},"4c68646b-0035-4279-8000-0006b275d4fa","Aghaee N, Peng Z, Eles P (2015) A test-ordering based temperature-cycling acceleration technique for 3D stacked ICs. Electron Test 33(5–6):503–523","https:\u002F\u002Flink.springer.com\u002F10.1007\u002Fs10440-022-00541-7",{"doi":716},"10.1007\u002Fs10440-022-00541-7",{"id":712,"text":718,"url":714,"identifiers":719},"Bhatia A, Hofmeister JP, Judkins J, Goodman D (2010) Advanced testing and prognostics of ball grid array components with a stand-alone monitor IC. IEEE Instrum Meas Mag 13(4):42–47",{"doi":716},{"id":712,"text":721,"url":714,"identifiers":722},"Constable JH, Lizzul C (1995) An investigation of solder joint fatigue using electrical resistance spectroscopy. IEEE Trans Compon Packag Manuf Technol Part A 18(1):142–152",{"doi":716},{"id":20,"text":724,"url":725,"identifiers":726},"Device Reliability Report Second Half 2014 (V10.2.1) (2015) http:\u002F\u002Fchina.xilinx.com\u002Fsupport\u002Fdocumentation\u002Fuser_guides\u002Fug116.pdf","http:\u002F\u002Fchina.xilinx.com\u002Fsupport\u002Fdocumentation\u002Fuser_guides\u002Fug116.pdf",{},{"id":712,"text":728,"url":714,"identifiers":729},"Duana N, Bachb T, Shena J, Rongena R (2014) Comparison of in-situ measurement techniques of solder joint reliability under thermo-mechanical stresses. Microelectron Reliab 54(9–10):1753–1757",{"doi":716},{"id":712,"text":731,"url":714,"identifiers":732},"Gershman I, Bernstein JB (2012) Structural health monitoring of solder joints in QFN package. Microelectron Reliab 52:3011–3016",{"doi":716},{"id":712,"text":734,"url":714,"identifiers":735},"Hofmeister JP, Lall P, Graves R (2006) In-situ, real-time detector for faults in solder joint networks belonging to operational, fully programmed field programmabmle gate arrays (FPGAs). In: Proc. IEEE Autotestcon, pp 237–243",{"doi":716},{"id":712,"text":737,"url":714,"identifiers":738},"Hofmeister JP, Lall P, Ortiz E, Goodman D, Judkins J (2007) Real-time detection of solder-joint faults in operational field programmable gate arrays. In: Proc. IEEE Aerospace Conference, pp 1–9",{"doi":716},{"id":712,"text":740,"url":714,"identifiers":741},"Hofmeister JP, Lall P, Roth N, Tracy T, Judkins J, Harris K (2008) Ball grid array (BGA) solder joint intermittency detection: SJ BIST. In: Proc. IEEE Aerospace Conference, pp 1–11",{"doi":716},{"id":743,"text":744,"url":745,"identifiers":746},"e47afd2d-eccd-413b-b29a-f0d7910368f4","Lee JH, Jeong H-Y (2014) Fatigue life prediction of solder joints with consideration of frequency, temperature and cracking energy density. Int J Fatigue 61:264–270","https:\u002F\u002Fwww.sciencedirect.com\u002Fscience\u002Farticle\u002Fpii\u002FS014211231300306X",{"doi":747},"10.1016\u002Fj.ijfatigue.2013.10.021",{"id":712,"text":749,"url":714,"identifiers":750},"Lin P, Lv X, Ding Y (2017) Study on the solder joint reliability of plastic ball grid array package for high reliability application. In: proc. IEEE 18th international conference on electronic packaging technology",{"doi":716},{"id":712,"text":752,"url":714,"identifiers":753},"Liu Y, Sun F, Zhang H, Wang J, Zhou Z (2014) Evaluating board level solder interconnects reliability using vibration test methods. Microelectron Reliab 54(9):2053–2057",{"doi":716},{"id":755,"text":756,"url":757,"identifiers":758},"dddf1e4a-b2c2-4bb5-b98c-0dd171d3776f","Liu C, Wang J, Zhang A, Ding H (2014) Research on the fault diagnosis technology of intermittent connection failure belonging to FPGA solder-joints in BGA package. Optik 125:737–740","https:\u002F\u002Fwww.sciencedirect.com\u002Fscience\u002Farticle\u002Fpii\u002FS0030402613010127",{"doi":759},"10.1016\u002Fj.ijleo.2013.07.044",{"id":712,"text":761,"url":714,"identifiers":762},"Roth N, Wondrak W, Willikens A, Hofmeister J (2008) Ball grid array (BGA) solder joint intermittency real-time detection. Microelectron Reliab 48:1155–1160",{"doi":716},{"id":712,"text":764,"url":714,"identifiers":765},"Shang Y, Sun L, Li C, Ma J (2007) Test of mechanical failure for via holes and solder joints of complex interconnect structure. Electron Test 33(4):491–499",{"doi":716},{"id":20,"text":767,"url":20,"identifiers":768},"Wang J, Ding H, Liu C, Liang Q (2014) Research on the fault diagnosis technology of connection failure belonging to the FPGA solder joint. Trans China Weld Inst 35(8):76–80 (In Chinese)",{},{"id":770,"text":771,"url":772,"identifiers":773},"71c9738e-f56d-43a6-9673-89e1cc27ea37","Wang N, Li Y, Yu Z, Ren Z (2015) Online test method of FPGA solder joint resistance with low power consumption. Microelectron Reliab 55(9–10):1867–1871","https:\u002F\u002Fwww.sciencedirect.com\u002Fscience\u002Farticle\u002Fpii\u002FS0026271415001390",{"doi":774},"10.1016\u002Fj.microrel.2015.06.009",{"id":776,"createTime":777,"updateTime":778,"relativeEntities":779,"slug":780,"properties":781,"entityType":190,"verifyStatus":191,"verifyTime":789,"verifyNote":193,"languages":20,"translateLanguages":20,"viewCount":21,"primaryUrl":790,"fullTextUrl":20,"authors":791,"publicationType":244,"publisherRelationship":820,"citationCount":20,"citationInfo":20,"publishDate":868,"publishYear":869,"citationAnalyzeStatus":400,"lastCitationAnalyze":778,"indexDatabases":870,"openAccess":20,"references":20,"isForceReanalyzing":299},"e8152790-7fd7-49e8-8147-41ffe0ca3636","2024-01-03T05:40:49.598+00:00","2026-07-16T13:57:18.512+00:00",[],"On-Using-Exponential-Golomb-Codes-and-Subexponential-Codes-for-System-on-a-Chip-Test-Data-Compression",{"abstract":782,"title":784,"gsPaper":786,"doi":787},{"EN":783},"We examine the use of exponential-Golomb codes and subexponential codes can be used for the compression of scan test data in core-based system-on-a-chip (SOC) designs. These codes are well-known in the data compression domain but their application to SOC testing has not been explored before. We show that these codes often provide slighly higher compression than alternative methods that have been proposed recently.",{"EN":785},"On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression",{"VOID":312},{"VOID":788},"10.1007\u002Fs10677-004-4254-0","2024-06-26T10:10:43.993+00:00","https:\u002F\u002Flink.springer.com\u002Farticle\u002F10.1007\u002Fs10677-004-4254-0",[792,807],{"id":793,"sortIndex":21,"researcher":20,"roles":794,"affiliations":795,"properties":804,"displayName":806,"givenName":20,"familyName":20},"f4f87da9-e638-465d-b983-e830c6669519",[199],[796],{"id":797,"sortIndex":21,"affiliation":798,"properties":20},"71462239-64f0-45e4-8fd3-53a70ff4285e",{"id":797,"createTime":20,"updateTime":20,"relativeEntities":799,"slug":20,"properties":800,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":803,"statistic":20},[],{"title":801},{"VI":802},"Department of Electrical and Computer Engineering, Duke University, Durham, USA",[],{"title":805},{"VI":806},"Lei Li",{"id":808,"sortIndex":91,"researcher":20,"roles":809,"affiliations":810,"properties":817,"displayName":819,"givenName":20,"familyName":20},"ad06a6dc-f289-458d-9f02-63df9faad35e",[199],[811],{"id":797,"sortIndex":21,"affiliation":812,"properties":20},{"id":797,"createTime":20,"updateTime":20,"relativeEntities":813,"slug":20,"properties":814,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":816,"statistic":20},[],{"title":815},{"VI":802},[],{"title":818},{"VI":819},"Krishnendu Chakrabarty",{"url":790,"publisher":821,"properties":863},{"id":6,"createTime":7,"updateTime":8,"relativeEntities":822,"slug":10,"properties":823,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":827,"manageAffiliations":832,"indexDatabases":843,"url":20,"thumbnailPath":20,"statistic":858,"gsStatistic":20,"type":20,"analyzePriority":20},[],{"issn":824,"title":825,"eissn":826},{"VOID":13},{"EN":15},{"VOID":17},[828],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":829,"label":830,"description":831,"parentId":20,"standard":20,"scholarHubFieldId":20},[],{"EN":27},{},[833,838],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":834,"slug":20,"properties":835,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":837,"statistic":20},[],{"title":836},{"EN":35},[37],{"id":39,"createTime":20,"updateTime":20,"relativeEntities":839,"slug":20,"properties":840,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":842,"statistic":20},[],{"title":841},{"EN":43},[],[844,851],{"id":47,"indexDatabase":845,"url":58,"indexYears":59,"academicFieldIds":850,"indexDatabaseRanking":62},{"id":49,"createTime":20,"updateTime":20,"relativeEntities":846,"label":847,"description":848,"key":55,"publicationTags":849,"standard":20},[],{"EN":52,"VI":52},{"EN":52,"VI":54},[57],[61],{"id":64,"indexDatabase":852,"url":77,"indexYears":20,"academicFieldIds":857,"indexDatabaseRanking":20},{"id":66,"createTime":20,"updateTime":20,"relativeEntities":853,"label":854,"description":855,"key":73,"publicationTags":856,"standard":20},[],{"EN":69,"VI":69},{"EN":71,"VI":72},[75,76],[79],{"impactFactor":21,"impactFactorByYear":859,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":860,"totalCitation":117,"totalCitationByYear":861,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":862,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},{"pages":864,"volume":866},{"VOID":865},"667-670",{"VOID":867},"20","2004-12-01",2004,[62,75],{"id":872,"createTime":873,"updateTime":874,"relativeEntities":875,"slug":876,"properties":877,"entityType":190,"verifyStatus":191,"verifyTime":886,"verifyNote":193,"languages":20,"translateLanguages":20,"viewCount":21,"primaryUrl":887,"fullTextUrl":20,"authors":888,"publicationType":244,"publisherRelationship":921,"citationCount":969,"citationInfo":970,"publishDate":973,"publishYear":971,"citationAnalyzeStatus":19,"lastCitationAnalyze":874,"indexDatabases":974,"openAccess":20,"references":975,"isForceReanalyzing":299},"57dc403d-5ef7-4abc-801c-c2e30ebb83d6","2023-12-13T09:02:06.922+00:00","2026-07-11T22:43:47.000+00:00",[],"Security-Path-An-Emerging-Design-Methodology-to-Protect-the-FPGA-IPs-Against-Passive-Active-Design-Tampering",{"abstract":878,"title":880,"gsPaper":882,"doi":884},{"EN":879},"Modern FPGAs have a great market share in hardware prototyping, massive parallel systems and reconfigurable architectures. Although the field-programmability of FPGAs is an effective feature in the growth and diversity of their applications; it has caused security concerns for IPs\u002FDesigns on FPGAs. Recent researches show that a reliable mechanism is required to protect the IPs\u002Fapplications on FPGAs against malicious manipulations during all stages of design lifecycle, especially when they are operating in the field. In this paper, we propose a new tamper-resistant design methodology (Security Path methodology) and a revised security-aware FPGA architecture. This methodology protects the configured design against tampering attacks in parallel with the normal operation of the circuit. When the attack is discovered, the normal data flow is obfuscated and the circuit is blocked. Experimental results show that this methodology provides near full coverage in tampering detection with overhead of 12.32 % in power, 12 % in delay and 38 % in area.",{"EN":881},"Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive\u002FActive Design Tampering",{"VOID":883},"[\"10624472909202243772\"]",{"VOID":885},"10.1007\u002Fs10836-016-5593-1","2024-04-24T11:50:16.525+00:00","http:\u002F\u002Flink.springer.com\u002F10.1007\u002Fs10836-016-5593-1",[889,906],{"id":890,"sortIndex":21,"researcher":20,"roles":891,"affiliations":892,"properties":901,"displayName":903,"givenName":20,"familyName":20},"98177072-06c0-4385-a1a7-58efc4d44416",[199],[893],{"id":894,"sortIndex":21,"affiliation":895,"properties":20},"4a0a0c04-def0-4db4-8fe0-fa2ca208cf2d",{"id":894,"createTime":20,"updateTime":20,"relativeEntities":896,"slug":20,"properties":897,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":900,"statistic":20},[],{"title":898},{"VI":899},"Faculty of Computer Science and Engineering, Shahid Beheshti University G.C., Tehran, Iran",[],{"title":902,"gsAuthor":904},{"VI":903},"Sharareh Zamanzadeh",{"VOID":905},"[\"MSRA1GEAAAAJ\"]",{"id":907,"sortIndex":91,"researcher":20,"roles":908,"affiliations":909,"properties":916,"displayName":918,"givenName":20,"familyName":20},"50f5f17b-617e-4ff0-911f-b66c14b08953",[199],[910],{"id":894,"sortIndex":21,"affiliation":911,"properties":20},{"id":894,"createTime":20,"updateTime":20,"relativeEntities":912,"slug":20,"properties":913,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":915,"statistic":20},[],{"title":914},{"VI":899},[],{"title":917,"gsAuthor":919},{"VI":918},"Ali Jahanian",{"VOID":920},"[\"gTht4nwAAAAJ\"]",{"url":887,"publisher":922,"properties":964},{"id":6,"createTime":7,"updateTime":8,"relativeEntities":923,"slug":10,"properties":924,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":928,"manageAffiliations":933,"indexDatabases":944,"url":20,"thumbnailPath":20,"statistic":959,"gsStatistic":20,"type":20,"analyzePriority":20},[],{"issn":925,"title":926,"eissn":927},{"VOID":13},{"EN":15},{"VOID":17},[929],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":930,"label":931,"description":932,"parentId":20,"standard":20,"scholarHubFieldId":20},[],{"EN":27},{},[934,939],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":935,"slug":20,"properties":936,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":938,"statistic":20},[],{"title":937},{"EN":35},[37],{"id":39,"createTime":20,"updateTime":20,"relativeEntities":940,"slug":20,"properties":941,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":943,"statistic":20},[],{"title":942},{"EN":43},[],[945,952],{"id":47,"indexDatabase":946,"url":58,"indexYears":59,"academicFieldIds":951,"indexDatabaseRanking":62},{"id":49,"createTime":20,"updateTime":20,"relativeEntities":947,"label":948,"description":949,"key":55,"publicationTags":950,"standard":20},[],{"EN":52,"VI":52},{"EN":52,"VI":54},[57],[61],{"id":64,"indexDatabase":953,"url":77,"indexYears":20,"academicFieldIds":958,"indexDatabaseRanking":20},{"id":66,"createTime":20,"updateTime":20,"relativeEntities":954,"label":955,"description":956,"key":73,"publicationTags":957,"standard":20},[],{"EN":69,"VI":69},{"EN":71,"VI":72},[75,76],[79],{"impactFactor":21,"impactFactorByYear":960,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":961,"totalCitation":117,"totalCitationByYear":962,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":963,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},{"pages":965,"volume":967},{"VOID":966},"329-343",{"VOID":968},"32",5,{"total":969,"publishYear":971,"statisticByYear":972},2016,{"2017":91,"2019":91,"2020":91,"2021":91,"2023":91},"2016-05-28",[62,75],[976,979,982,985,989,992,995,998,1001,1004,1007,1011,1014,1017,1020,1023,1026,1029,1032,1035,1039,1042,1045,1048,1051,1055,1059],{"id":20,"text":977,"url":20,"identifiers":978},"Altera Corporation (2014) Altera unique chip ID IP core user guide. ug-altchipid",{},{"id":712,"text":980,"url":714,"identifiers":981},"Chakraborty RS, Saha I, Palchaudhuri A (2013) Hardware Trojan insertion by direct modification of FPGA configuration bitstream. IEEE Des Test 30(2):45–54",{"doi":716},{"id":20,"text":983,"url":20,"identifiers":984},"Hori Y, Katashita T, Sasaki A (2012) Electromagnetic side-channel attack against 28-nm FPGA device. In: International workshop on information security applications, pp 16–18",{},{"id":20,"text":986,"url":987,"identifiers":988},"Hutton M, Lewis D, Pedersen B (2006) Fracturable FPGA logic elements, CP-01006-1.0 http:\u002F\u002Fwww.altera.Com\u002Fliterature\u002Fcp\u002Fcp-01006.pdf, Tech. Rep.","http:\u002F\u002Fwww.altera.Com\u002Fliterature\u002Fcp\u002Fcp-01006.pdf",{},{"id":712,"text":990,"url":714,"identifiers":991},"Kastensmidt F, Carro L, Reis R (2006) Fault-tolerance techniques for SRAM-based FPGAs. In: Series: frontiers in electronic testing, vol 32. Springer, pp 180–185",{"doi":716},{"id":20,"text":993,"url":20,"identifiers":994},"Lu T, Kenny R, Atsatt S (2015) Stratix 10 secure device manager provides best-in-class FPGA and SoC security. White paper, WP-01252-10",{},{"id":712,"text":996,"url":714,"identifiers":997},"Luu J, Anderson J, Rose J (2011) Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. In: Proceedings of the 19th ACM\u002FSIGDA international symposium on field programmable gate arrays, pp 227–236",{"doi":716},{"id":20,"text":999,"url":20,"identifiers":1000},"McNeil S (2012) Solving today’s design security concerns. Xilinx, White paper, WP365 (v1.2) July 30",{},{"id":712,"text":1002,"url":714,"identifiers":1003},"Moradi A, Barenghi A, Kasper T, Paar C (2011) On the vulnerability of FPGA bitstream encryption against power analysis attacks: Extracting keys from Xilinx Virtex-II FPGAs. In: Proceedings of ACM conference on computer and communications security, pp 111–124",{"doi":716},{"id":712,"text":1005,"url":714,"identifiers":1006},"Moradi A, Barenghi A, Paar C (2011) On the vulnerability of FPGA bitstream encryption against power analysis attacks. In: Proceedings of the 18th ACM conference on computer and communications security. ACM, pp 111–123",{"doi":716},{"id":20,"text":1008,"url":20,"identifiers":1009},"Moradi A, Kasper M, Parr C (2012) Black-box side-channel attacks highlight the importance of countermeasuresVAn analysis of the Xilinx Virtex 4 and Virtex-5 bitstream encryption mechanism. In: Proceedings of the 12th conference topics in cryptology doi:10.1007\u002F978-3-642-27954-6_1",{"doi":1010},"10.1007\u002F978-3-642-27954-6_1",{"id":712,"text":1012,"url":714,"identifiers":1013},"Moradi A, Oswald D, Paar C, Swierczynski P (2013) Side channel attacks on the bitstream encryption mechanism of Altera Stratix II. In: Proceedings of the ACM\u002FSIGDA international symposium on field-programmable gate arrays, pp 91–100",{"doi":716},{"id":712,"text":1015,"url":714,"identifiers":1016},"Mudler E, Buysschaert P, Delmotte P (2005) Electromagnetic analysis attack on an FPGA implementation of an elliptic curve cryptosystem. In: International conference on computer as a tool (EUROCON), pp 1879–1882",{"doi":716},{"id":712,"text":1018,"url":714,"identifiers":1019},"Note J, Rannaud E (2008) From the bitstream to the netlist. In: Proceedings of the 16th international ACM\u002FSIGDA symposium on field programmable gate arrays, pp 264–270",{"doi":716},{"id":20,"text":1021,"url":20,"identifiers":1022},"Peterson E (2013) Developing tamper resistant designs with Xilinx Virtex-6 and 7 series FPGAs. Xilinx, Appl, XAPP1084 (v13)",{},{"id":712,"text":1024,"url":714,"identifiers":1025},"Rajendran J, Zhang H, Karri R (2015) Fault analysis-based logic encryption. IEEE Trans Comput 64 (2):410–424",{"doi":716},{"id":712,"text":1027,"url":714,"identifiers":1028},"Rajendran J, Zhang H, Karri R et al (2015) Fault analysis-based logic encryption. IEEE Trans Comput 64(2):410–424",{"doi":716},{"id":20,"text":1030,"url":20,"identifiers":1031},"Rose J, Luu J, Goeders J (2014) VTR 7.0: next generation architecture and CAD system for FPGAs. In: ACM transaction on reconfigurable technology and systems (TRETS), vol 7, no 2",{},{"id":712,"text":1033,"url":714,"identifiers":1034},"Skorobogatov S, Woods C (2012) Breakthrough silicon scanning discovers backdoor in military chip. In: Cryptographic hardware and embedded systems VCHES 2012, vol 7428. Springer, Berlin, pp 23–40",{"doi":716},{"id":20,"text":1036,"url":1037,"identifiers":1038},"Stratix IV FPGA ALM Logic Structure’s Fracturable LUT (2015) Available on https:\u002F\u002Fwww.altera.com\u002Fproducts","https:\u002F\u002Fwww.altera.com\u002Fproducts",{},{"id":712,"text":1040,"url":714,"identifiers":1041},"Swierczynski P, Fyrbiak M, Paar C (2015) FPGA Trojans through detecting and weakening of cryptographic primitives. In: IEEE transactions on computer aided design, pp 1–13",{"doi":716},{"id":20,"text":1043,"url":20,"identifiers":1044},"Trimberger S, Moore J (2014) FPGA security: from features to capabilities to trusted systems. In: Design automation conference DAC’14, pp 1–4",{},{"id":712,"text":1046,"url":714,"identifiers":1047},"Trimberger SM, Moore J (2014) FPGA security: motivations, features, and applications. Invited paper in Proc IEEE 102(8):1248–1265",{"doi":716},{"id":712,"text":1049,"url":714,"identifiers":1050},"Vu TH, Cuong NV (2012) A framework for secure remote updating of bitstream of runtime reconfigurable embedded platforms. In: Communications and electronics, pp 471–476",{"doi":716},{"id":20,"text":1052,"url":1053,"identifiers":1054},"Xilinx Virtex-6 FPGA Configurable Logic Block User’s Guide (2014) Available on http:\u002F\u002Fwww.xilinx.com\u002Fsupport","http:\u002F\u002Fwww.xilinx.com\u002Fsupport",{},{"id":20,"text":1056,"url":1057,"identifiers":1058},"Xilinx Virtex-7 family overview (2015) Available on http:\u002F\u002Fwww.xilinx.com\u002Fproducts\u002Fsilicon-devices\u002Ffpga\u002F","http:\u002F\u002Fwww.xilinx.com\u002Fproducts\u002Fsilicon-devices\u002Ffpga\u002F",{},{"id":712,"text":1060,"url":714,"identifiers":1061},"Zhang J, Qu G (2014) A survey on security and trust of FPGA-based systems. In: International conference on field programmable technology (FPT), pp 147–152",{"doi":716},{"id":1063,"createTime":1064,"updateTime":1065,"relativeEntities":1066,"slug":1067,"properties":1068,"entityType":190,"verifyStatus":191,"verifyTime":1079,"verifyNote":193,"languages":1080,"translateLanguages":20,"viewCount":21,"primaryUrl":1082,"fullTextUrl":20,"authors":1083,"publicationType":244,"publisherRelationship":1173,"citationCount":21,"citationInfo":1223,"publishDate":1226,"publishYear":1224,"citationAnalyzeStatus":19,"lastCitationAnalyze":1227,"indexDatabases":1228,"openAccess":20,"references":1229,"isForceReanalyzing":299},"0d302524-b11e-419a-810f-4efbd0b2f663","2024-04-19T12:10:52.256+00:00","2026-07-11T07:15:47.705+00:00",[],"Bandwidth-Analysis-of-Functional-Interconnects-Used-as-Test-Access-Mechanism",{"openalex":1069,"mag":1071,"title":1073,"gsPaper":1075,"doi":1077},{"VOID":1070},"W2155388119",{"VOID":1072},"2155388119",{"EN":1074},"Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism",{"VOID":1076},"[\"15364722270248164834\"]",{"VOID":1078},"10.1007\u002Fs10836-010-5163-x","2024-06-24T14:16:55.796+00:00",[1081],"EN","http:\u002F\u002Flink.springer.com\u002F10.1007\u002Fs10836-010-5163-x",[1084,1103,1118,1139,1156],{"id":1085,"sortIndex":21,"researcher":20,"roles":1086,"affiliations":1087,"properties":1096,"displayName":1100,"givenName":20,"familyName":20},"690c2060-3547-4a34-937f-447eda01ff47",[],[1088],{"id":1089,"sortIndex":21,"affiliation":1090,"properties":20},"8cba3668-0f2b-427c-856c-c45e8f0b55db",{"id":1089,"createTime":20,"updateTime":20,"relativeEntities":1091,"slug":20,"properties":1092,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1095,"statistic":20},[],{"title":1093},{"EN":1094},"Department of Computer Engineering, Delft University of Technology, Mekelweg 4, 2628CD, Delft, The Netherlands",[],{"orcid":1097,"title":1099,"openalex":1101},{"VOID":1098},"https:\u002F\u002Forcid.org\u002F0000-0003-2991-9478",{"EN":1100},"A. van den Berg",{"VOID":1102},"A5072206217",{"id":1104,"sortIndex":91,"researcher":20,"roles":1105,"affiliations":1106,"properties":1113,"displayName":1115,"givenName":20,"familyName":20},"98177dec-ab05-4141-bb5d-e0b25f89bc65",[],[1107],{"id":1089,"sortIndex":21,"affiliation":1108,"properties":20},{"id":1089,"createTime":20,"updateTime":20,"relativeEntities":1109,"slug":20,"properties":1110,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1112,"statistic":20},[],{"title":1111},{"EN":1094},[],{"title":1114,"openalex":1116},{"EN":1115},"Pengwei Ren",{"VOID":1117},"A5079418163",{"id":1119,"sortIndex":139,"researcher":20,"roles":1120,"affiliations":1121,"properties":1130,"displayName":1134,"givenName":20,"familyName":20},"9bb12d09-8bd4-411c-9f30-af9033aba1ab",[],[1122],{"id":1123,"sortIndex":21,"affiliation":1124,"properties":20},"1a3224fd-c079-48ef-aed0-e86b49dd2fd6",{"id":1123,"createTime":20,"updateTime":20,"relativeEntities":1125,"slug":20,"properties":1126,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1129,"statistic":20},[],{"title":1127},{"EN":1128},"Corporate Innovation & Technology, NXP Semiconductors, High Tech Campus 37, 5656AE, Eindhoven, The Netherlands",[],{"orcid":1131,"title":1133,"gsAuthor":1135,"openalex":1137},{"VOID":1132},"https:\u002F\u002Forcid.org\u002F0000-0002-5058-8303",{"EN":1134},"Erik Jan Marinissen",{"VOID":1136},"[\"nYay1e0AAAAJ\"]",{"VOID":1138},"A5044629739",{"id":1140,"sortIndex":486,"researcher":20,"roles":1141,"affiliations":1142,"properties":1149,"displayName":1153,"givenName":20,"familyName":20},"19745e59-1bfb-48c0-a838-3eabceddbcf7",[],[1143],{"id":1089,"sortIndex":21,"affiliation":1144,"properties":20},{"id":1089,"createTime":20,"updateTime":20,"relativeEntities":1145,"slug":20,"properties":1146,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1148,"statistic":20},[],{"title":1147},{"EN":1094},[],{"orcid":1150,"title":1152,"openalex":1154},{"VOID":1151},"https:\u002F\u002Forcid.org\u002F0000-0002-3678-7007",{"EN":1153},"Georgi Gaydadjiev",{"VOID":1155},"A5075050234",{"id":1157,"sortIndex":138,"researcher":20,"roles":1158,"affiliations":1159,"properties":1166,"displayName":1170,"givenName":20,"familyName":20},"4ec5e902-62bb-4996-bd42-802a55c92c5a",[],[1160],{"id":1123,"sortIndex":21,"affiliation":1161,"properties":20},{"id":1123,"createTime":20,"updateTime":20,"relativeEntities":1162,"slug":20,"properties":1163,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1165,"statistic":20},[],{"title":1164},{"EN":1128},[],{"orcid":1167,"title":1169,"openalex":1171},{"VOID":1168},"https:\u002F\u002Forcid.org\u002F0000-0001-7536-4050",{"EN":1170},"Kees Goossens",{"VOID":1172},"A5048502768",{"url":20,"publisher":1174,"properties":1216},{"id":6,"createTime":7,"updateTime":8,"relativeEntities":1175,"slug":10,"properties":1176,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":1180,"manageAffiliations":1185,"indexDatabases":1196,"url":20,"thumbnailPath":20,"statistic":1211,"gsStatistic":20,"type":20,"analyzePriority":20},[],{"issn":1177,"title":1178,"eissn":1179},{"VOID":13},{"EN":15},{"VOID":17},[1181],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":1182,"label":1183,"description":1184,"parentId":20,"standard":20,"scholarHubFieldId":20},[],{"EN":27},{},[1186,1191],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":1187,"slug":20,"properties":1188,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1190,"statistic":20},[],{"title":1189},{"EN":35},[37],{"id":39,"createTime":20,"updateTime":20,"relativeEntities":1192,"slug":20,"properties":1193,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1195,"statistic":20},[],{"title":1194},{"EN":43},[],[1197,1204],{"id":47,"indexDatabase":1198,"url":58,"indexYears":59,"academicFieldIds":1203,"indexDatabaseRanking":62},{"id":49,"createTime":20,"updateTime":20,"relativeEntities":1199,"label":1200,"description":1201,"key":55,"publicationTags":1202,"standard":20},[],{"EN":52,"VI":52},{"EN":52,"VI":54},[57],[61],{"id":64,"indexDatabase":1205,"url":77,"indexYears":20,"academicFieldIds":1210,"indexDatabaseRanking":20},{"id":66,"createTime":20,"updateTime":20,"relativeEntities":1206,"label":1207,"description":1208,"key":73,"publicationTags":1209,"standard":20},[],{"EN":69,"VI":69},{"EN":71,"VI":72},[75,76],[79],{"impactFactor":21,"impactFactorByYear":1212,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":1213,"totalCitation":117,"totalCitationByYear":1214,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":1215,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},{"issue":1217,"pages":1219,"volume":1221},{"VOID":1218},"4",{"VOID":1220},"453-464",{"VOID":1222},"26",{"total":21,"publishYear":1224,"statisticByYear":1225},2010,{},"2010-08-01","2026-07-11T07:15:47.704+00:00",[62,75],[1230,1234,1238,1241,1244,1248,1252,1255,1258,1262,1266,1270,1274,1278,1282,1285,1289,1293,1296,1299,1302,1306,1310,1314,1318,1321,1325,1328,1332],{"id":20,"text":1231,"url":20,"identifiers":1232},"Amory AM, Cota É, Lubaszewski M, Moraes, FG (2004) Reducing test time with processor reuse in Network-on-Chip based systems. In: Proceedings Brazilian symposium on integrated circuits and system design (SBCCI). Pernambuco, Brazil, pp 111–116",{"doi":1233},"10.1145\u002F1016568.1016602",{"id":20,"text":1235,"url":20,"identifiers":1236},"Amory AM, Goossens K, Marinissen EJ, Lubaszewski M, Moraes FG (2007) Wrapper design for the reuse of a bus, Network-on-Chip, or other functional interconnect as Test Access Mechanism. IET Comput Dig Tech 1(3):197–206",{"doi":1237},"10.1049\u002Fiet-cdt:20060152",{"id":20,"text":1239,"url":20,"identifiers":1240},"Amory AM, Oliveira LA, Moraes FG (2003) Software-based test for non-programmable cores in bus-based system-on-chip architectures. In: Proceedings IFIP international conference on very large scale integration (VLSI-SOC). Darmstadt, Germany, pp 174–179",{},{"id":20,"text":1242,"url":20,"identifiers":1243},"ARM (2003) AMBA AXI protocol specification",{},{"id":20,"text":1245,"url":20,"identifiers":1246},"Cota E, Carro L, Lubaszewski M (2004) Reusing an on-chip network for the test of core-based systems. ACM Transact Des Automat Electron Syst 9(4):471–499",{"doi":1247},"10.1145\u002F1027084.1027088",{"id":20,"text":1249,"url":20,"identifiers":1250},"Cota E, Kreutz M, Zeferino CA, Carro L, Lubaszewski M, Susin A (2003) The impact of NoC reuse on the testing of core-based systems. In: Proceedings IEEE VLSI test symposium (VTS). Napa, CA, USA, pp 128–133",{"doi":1251},"10.1109\u002FVTEST.2003.1197643",{"id":20,"text":1253,"url":20,"identifiers":1254},"DaSilva F (ed) (2005) IEEE Std 1500TM-2005. IEEE standard testability method for embedded core-based integrated circuits. IEEE, New York",{},{"id":20,"text":1256,"url":20,"identifiers":1257},"De Micheli G, Benini L (eds) (2006) Networks on chips: technology and tools. The Morgan Kaufmann series in systems on silicon. Morgan Kaufmann",{},{"id":20,"text":1259,"url":20,"identifiers":1260},"Feige C, ten Pierick J, Wouters C, Tangelder R, Kerkhoff HG (1999) Integration of the scan-test method into an architecture specific core-test approach. J Electron Test: Theory and Applications 14(1–2):125–131",{"doi":1261},"10.1023\u002FA:1008313726031",{"id":20,"text":1263,"url":20,"identifiers":1264},"Goel SK, Marinissen EJ (2003) SOC test architecture design for efficient utilization of test bandwidth. ACM Transact Des Automat Electron Syst 8(4):399–429",{"doi":1265},"10.1145\u002F944027.944029",{"id":20,"text":1267,"url":20,"identifiers":1268},"Goossens K, Dielissen J, Gangwal OP, Pestana SG, Rădulescu A, Rijpkema E (2005) A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. In: Proceedings design, automation, and test in Europe (DATE), Munich, Germany, pp 1182–1187",{"doi":1269},"10.1109\u002FDATE.2005.11",{"id":20,"text":1271,"url":20,"identifiers":1272},"Goossens K, Dielissen J, Rădulescu A (2005) The Æthereal network on chip: concepts, architectures, and implementations. IEEE Des Test Comput 22(5):414–421",{"doi":1273},"10.1109\u002FMDT.2005.99",{"id":20,"text":1275,"url":20,"identifiers":1276},"Hansson A, Goossens K, Rădulescu A (2007) A unified approach to mapping and routing on a network on chip for both best-effort and guaranteed service traffic. VLSI Des 2007: Article ID 68432. Hindawi Publishing Corporation, 16 pp",{"doi":1277},"10.1155\u002F2007\u002F68432",{"id":20,"text":1279,"url":20,"identifiers":1280},"Harrod P (1999) Testing reusable IP—a case study. In: Proceedings IEEE international test conference (ITC). Atlantic City, NJ, USA, pp 493–498",{"doi":1281},"10.1109\u002FTEST.1999.805772",{"id":20,"text":1283,"url":20,"identifiers":1284},"Huang J-R, Iyer MK, Cheng K-T (2001) A self-test methodology for IP cores in bus-based programmable SOCs. In: Proceedings IEEE VLSI test symposium (VTS). Marina del Rey, CA, USA, pp 198–203",{},{"id":20,"text":1286,"url":20,"identifiers":1287},"Hussin FA, Yoneda T, Fujiwara H (2007) Optimization of NoC wrapper design under bandwidth and test time constraints. In: Proceedings IEEE European test symposium (ETS). Freiburg, Germany, pp 35–42",{"doi":1288},"10.1109\u002FETS.2007.30",{"id":20,"text":1290,"url":20,"identifiers":1291},"Hussin FA, Yoneda T, Fujiwara H (2008) NoC-compatible wrapper design and optimization under channel-bandwidth and test-time constraints. IEICE Trans Inf Syst E91-D(7):2008–2017",{"doi":1292},"10.1093\u002Fietisy\u002Fe91-d.7.2008",{"id":20,"text":1294,"url":20,"identifiers":1295},"Hwang S, Abraham JA (2001) Reuse of addressable system bus for SOC testing. In: Proceedings IEEE international ASIC\u002FSOC conference, Arlington, VA, USA, pp 215–219",{},{"id":20,"text":1297,"url":20,"identifiers":1298},"Liu C, Link Z, Pradhan DK (2006) Reuse-based test access and integrated test scheduling for Network-on-Chip. In: Proceedings IEEE European test symposium (ETS), Southampton, UK, pp 303–308",{},{"id":20,"text":1300,"url":20,"identifiers":1301},"Marinissen EJ, Goel SK (2002) Analysis of test bandwidth utilization in test bus and TestRail architectures for SOCs. In: Proceedings IEEE design and diagnostics of electronic circuits and systems workshop (DDECS). Brno, Czech Republic, pp 52–60",{},{"id":20,"text":1303,"url":20,"identifiers":1304},"Marinissen EJ, Goel SK, Lousberg M (2000) Wrapper design for embedded core test. In: Proceedings IEEE international test conference (ITC). Atlantic City, NJ, USA, pp 911–920",{"doi":1305},"10.1109\u002FTEST.2000.894302",{"id":20,"text":1307,"url":20,"identifiers":1308},"Marinissen EJ, Iyengar V, Chakrabarty K (2002) A set of benchmarks for modular testing of SOCs. In: Proceedings IEEE international test conference (ITC). Baltimore, MD, USA, pp 519–528",{"doi":1309},"10.1109\u002FTEST.2002.1041802",{"id":20,"text":1311,"url":20,"identifiers":1312},"Nahvi M, Ivanov A (2001) A packet switching communication-based Test Access Mechanism for system chips. In: Digest of papers of IEEE European test workshop (ETW). Saltsjöbaden, Sweden, pp 195–200",{"doi":1313},"10.1109\u002FETW.2001.946668",{"id":20,"text":1315,"url":20,"identifiers":1316},"Nolen JM, Mahapatra RN (2008) Time-division-multiplexed test delivery for NoC systems. IEEE Des Test Comput 25(1):44–51",{"doi":1317},"10.1109\u002FMDT.2008.27",{"id":20,"text":1319,"url":20,"identifiers":1320},"Philips Semiconductors (2002) Device transaction level (DTL) protocol specification. Version 2.2",{},{"id":20,"text":1322,"url":20,"identifiers":1323},"Rădulescu A, Dielissen J, Pestana SG, Gangwal OP, Rijpkema E, Wielage P, Goossens K (2005) An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming. IEEE Trans Comput-Aided Des Integr Circuits Syst 24(1):4–17",{"doi":1324},"10.1109\u002FTCAD.2004.839493",{"id":20,"text":1326,"url":20,"identifiers":1327},"van den Berg A (2007) Automation of wrapper design for the reuse of a bus, Network-on-Chip, or other functional interconnect as Test Access Mechanism in a chip. MSc Thesis, Delft University of Technology, The Netherlands",{},{"id":20,"text":1329,"url":20,"identifiers":1330},"van den Berg A, Ren P, Marinissen EJ, Goossens K, Gaydadjiev G (2008) Bandwidth analysis for reusing functional interconnect as Test Access Mechanism. In: Proceedings IEEE European test symposium (ETS). Lago Maggiore, Italy, pp 21–26",{"doi":1331},"10.1109\u002FETS.2008.34",{"id":20,"text":1333,"url":20,"identifiers":1334},"Zorian Y, Marinissen EJ, Dey S (1998) Testing embedded-core based system chips. In: Proceedings IEEE international test conference (ITC). Washington, DC, USA, pp 130–143",{"doi":1335},"10.1109\u002FTEST.1998.743146",{"id":1337,"createTime":1338,"updateTime":1339,"relativeEntities":1340,"slug":1341,"properties":1342,"entityType":190,"verifyStatus":191,"verifyTime":1351,"verifyNote":193,"languages":20,"translateLanguages":20,"viewCount":21,"primaryUrl":1352,"fullTextUrl":20,"authors":1353,"publicationType":244,"publisherRelationship":1405,"citationCount":139,"citationInfo":1453,"publishDate":1456,"publishYear":1454,"citationAnalyzeStatus":19,"lastCitationAnalyze":1339,"indexDatabases":1457,"openAccess":20,"references":1458,"isForceReanalyzing":299},"260ae4f1-8a23-4247-8019-31df175c943b","2024-01-04T13:31:58.027+00:00","2026-07-11T04:52:51.203+00:00",[],"GPUs-Neutron-Sensitivity-Dependence-on-Data-Type",{"abstract":1343,"title":1345,"gsPaper":1347,"doi":1349},{"EN":1344},"Graphics Processing Units are very prone to be corrupted by neutrons. Experimental results obtained irradiating the GPU with high energy neutrons show that the input data type has a strong influence on the neutron-induced error-rate of the executed algorithms. Moreover, when operations are performed using floating-point data, the probabilities to be corrupted are very different for the mantissa, the exponent or the sign. We investigate the occurrences of errors in the different positions, evaluating the related effects on the result precision. The reported results and the architecture analysis demonstrate that under radiation, whenever possible, one should favor floating-point arithmetic, which is both more reliable and potentially easier to protect than the integer one.",{"EN":1346},"GPUs Neutron Sensitivity Dependence on Data Type",{"VOID":1348},"[\"6359492422137933391\"]",{"VOID":1350},"10.1007\u002Fs10836-014-5456-6","2024-04-27T07:35:04.841+00:00","https:\u002F\u002Flink.springer.com\u002Farticle\u002F10.1007\u002Fs10836-014-5456-6",[1354,1371,1388],{"id":1355,"sortIndex":21,"researcher":20,"roles":1356,"affiliations":1357,"properties":1366,"displayName":1368,"givenName":20,"familyName":20},"fecdd362-13b8-4b05-af40-7fd3178a7e05",[199],[1358],{"id":1359,"sortIndex":21,"affiliation":1360,"properties":20},"a25d6251-ff54-4a39-abb9-d91c136405d0",{"id":1359,"createTime":20,"updateTime":20,"relativeEntities":1361,"slug":20,"properties":1362,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1365,"statistic":20},[],{"title":1363},{"VI":1364},"Departamento de Informatica Aplicada, Instituto de Informatica, Universitade Federal do Rio Grande do Sul, Porto Alegre, Brasil",[],{"title":1367,"gsAuthor":1369},{"VI":1368},"P. Rech",{"VOID":1370},"[\"1EKLRakAAAAJ\"]",{"id":1372,"sortIndex":91,"researcher":20,"roles":1373,"affiliations":1374,"properties":1383,"displayName":1385,"givenName":20,"familyName":20},"23e80ccb-d6d3-4e91-997b-91f713f45e55",[199],[1375],{"id":1376,"sortIndex":21,"affiliation":1377,"properties":20},"5beebb45-1da0-4d6d-9136-ec02c1e87eaa",{"id":1376,"createTime":20,"updateTime":20,"relativeEntities":1378,"slug":20,"properties":1379,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1382,"statistic":20},[],{"title":1380},{"VI":1381},"Rutherford Appleton Laboratories, STFC, Didcot, UK",[],{"title":1384,"gsAuthor":1386},{"VI":1385},"C. Frost",{"VOID":1387},"[\"ackb6joAAAAJ\"]",{"id":1389,"sortIndex":139,"researcher":20,"roles":1390,"affiliations":1391,"properties":1400,"displayName":1402,"givenName":20,"familyName":20},"ac15b4a1-8b89-473f-b55d-38e54813ef69",[199],[1392],{"id":1393,"sortIndex":21,"affiliation":1394,"properties":20},"2f5aca43-46e3-4ef1-b0be-fe75ea19c1d1",{"id":1393,"createTime":20,"updateTime":20,"relativeEntities":1395,"slug":20,"properties":1396,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1399,"statistic":20},[],{"title":1397},{"VI":1398},"Universitade Federal do Rio Grande do Sul, Porto Alegre, Brazil",[],{"title":1401,"gsAuthor":1403},{"VI":1402},"L. Carro",{"VOID":1404},"[\"vS6vkY4AAAAJ\"]",{"url":1352,"publisher":1406,"properties":1448},{"id":6,"createTime":7,"updateTime":8,"relativeEntities":1407,"slug":10,"properties":1408,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":1412,"manageAffiliations":1417,"indexDatabases":1428,"url":20,"thumbnailPath":20,"statistic":1443,"gsStatistic":20,"type":20,"analyzePriority":20},[],{"issn":1409,"title":1410,"eissn":1411},{"VOID":13},{"EN":15},{"VOID":17},[1413],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":1414,"label":1415,"description":1416,"parentId":20,"standard":20,"scholarHubFieldId":20},[],{"EN":27},{},[1418,1423],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":1419,"slug":20,"properties":1420,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1422,"statistic":20},[],{"title":1421},{"EN":35},[37],{"id":39,"createTime":20,"updateTime":20,"relativeEntities":1424,"slug":20,"properties":1425,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1427,"statistic":20},[],{"title":1426},{"EN":43},[],[1429,1436],{"id":47,"indexDatabase":1430,"url":58,"indexYears":59,"academicFieldIds":1435,"indexDatabaseRanking":62},{"id":49,"createTime":20,"updateTime":20,"relativeEntities":1431,"label":1432,"description":1433,"key":55,"publicationTags":1434,"standard":20},[],{"EN":52,"VI":52},{"EN":52,"VI":54},[57],[61],{"id":64,"indexDatabase":1437,"url":77,"indexYears":20,"academicFieldIds":1442,"indexDatabaseRanking":20},{"id":66,"createTime":20,"updateTime":20,"relativeEntities":1438,"label":1439,"description":1440,"key":73,"publicationTags":1441,"standard":20},[],{"EN":69,"VI":69},{"EN":71,"VI":72},[75,76],[79],{"impactFactor":21,"impactFactorByYear":1444,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":1445,"totalCitation":117,"totalCitationByYear":1446,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":1447,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},{"pages":1449,"volume":1451},{"VOID":1450},"307-316",{"VOID":1452},"30",{"total":139,"publishYear":1454,"statisticByYear":1455},2014,{},"2014-06-14",[62,75],[1459,1462,1465,1468,1471,1474,1477,1480,1483,1486,1489,1492,1495,1498,1501,1504,1507,1510,1513,1516],{"id":712,"text":1460,"url":714,"identifiers":1461},"Baumann R C (2005) Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans Dev Mater Reliab 5(3):305–316",{"doi":716},{"id":712,"text":1463,"url":714,"identifiers":1464},"Di Carlo S et al (2013) A software-based self test of CUDA fermi GPUs. IEEE Eur Test Symp: 3338",{"doi":716},{"id":712,"text":1466,"url":714,"identifiers":1467},"Haque I S, Pande V S (2010) Hard data on soft errors: a large- scale assessment of real-world error-rates in GPGPU. In: Proceedings of the IEEE\u002FACM international conference on cluster, cloud and grid computing, pp 691–696",{"doi":716},{"id":712,"text":1469,"url":714,"identifiers":1470},"Kim S-H et al (2007) A low power and highly reliable 400Mbps mobile DDR SDRAM with on-chip distributed ECC. In: Proceedings of IEEE Asian solid-state circuits conference. pp 34–37",{"doi":716},{"id":20,"text":1472,"url":20,"identifiers":1473},"Kirk DB, Hwo WW Programming massively parallel processors. MK Publishers",{},{"id":712,"text":1475,"url":714,"identifiers":1476},"Kruger J, Westermann R (2003) Linear algebra operators for GPU implementation of numerical algorithms. ACM Trans Graph 3(22):908–916",{"doi":716},{"id":712,"text":1478,"url":714,"identifiers":1479},"Liepe J, Barnes C, Cule E, Erguler K, Kirk P, Toni T, Stumpf M P H (2012) ABC-SysBio-approximate Bayesian computation in Python with GPU support. Bioinformatics 26(14):1797–1799",{"doi":716},{"id":712,"text":1481,"url":714,"identifiers":1482},"Lindholm E, Nickolls J, Oberman S, Montrym J (2008) NVIDIA Tesla: a unified graphics and computing architecture. IEEE MICRO 28(2):39–55",{"doi":716},{"id":712,"text":1484,"url":714,"identifiers":1485},"Nguyen HT, Yagil Y, Seifert N, Reitsma M (2005) Chip-level soft error estimation method. IEEE Trans Dev Mater Reliab 5(3):356–381",{"doi":716},{"id":20,"text":1487,"url":20,"identifiers":1488},"NVIDIA GeForce GTX 480\u002F470\u002F465 GPU Datasheet",{},{"id":20,"text":1490,"url":20,"identifiers":1491},"Owens JD, Houston M, Luebke D, Green S, Stone JE, Phillips JC (2008) GPU Computing. Proc IEEE 96(5):879–899",{},{"id":712,"text":1493,"url":714,"identifiers":1494},"Pilla LL, Rech P, Silvestri F, Frost C, Navaux P O A, Sonza Reorda M, Carro L (2014) Software-based hardening strategies for neutron sensitive FFT algorithms on GPUs. IEEE Trans Nucl Sci 99:1–7",{"doi":716},{"id":712,"text":1496,"url":714,"identifiers":1497},"Rech P, Aguiar C, Frost C, Carro L (2012) Neutron radiation test of graphic processing units. In: Proceedings IEEE IOLTS",{"doi":716},{"id":712,"text":1499,"url":714,"identifiers":1500},"Rech P, Aguiar C, Ferreira R, Silvestri M, Griffoni A, Frost C, Carro L (2012) Neutron-induced soft error in graphic processing units. In: Proceedings of IEEE REDW",{"doi":716},{"id":712,"text":1502,"url":714,"identifiers":1503},"Rech P, Aguiar C, Frost C, Carro L An efficient and experimentally tuned software-based hardening strategy for matrix multiplication on GPUs. IEEE Trans Nucl Sci 60(4):2797–2804",{"doi":716},{"id":712,"text":1505,"url":714,"identifiers":1506},"Sheaffer JW, Luebke DP, Skadron K (2007) A hardware redundancy and recovery mechanism for reliable scientific computation on graphics processors. In: Proceedings of the ACM SIGGRAPH symposium on graphics hardware (GH). pp 55–64",{"doi":716},{"id":20,"text":1508,"url":20,"identifiers":1509},"Seifert N, Xiaowei Z, Massengill L W Impact of scaling on soft-error-rates in commercial microprocessors, vol 46",{},{"id":712,"text":1511,"url":714,"identifiers":1512},"Shi G, Enos J, Showerman M, Kindratenko V (2009) On testing GPU memory for hard and soft errors. In: Proceedings of the symposium on application accelerators in high-performance computing (SAAHPC)",{"doi":716},{"id":712,"text":1514,"url":714,"identifiers":1515},"Violante M et al A New hardware\u002Fsoftware platform and a new 1\u002FE neutron source for soft error studies: testing FPGAs at the ISIS facility. IEEE TNS Nucl Sci 54(4):1184–1189",{"doi":716},{"id":712,"text":1517,"url":714,"identifiers":1518},"Wang NJ, Quek J, Rafacz TM, Patel SJ (2004) Characterizing the effects of transient faults on a high-performance processor pipeline. In: Proceedings of the IEEE international conference on dependable systems and networks (DSN). pp 61–70",{"doi":716},{"id":1520,"createTime":1521,"updateTime":1522,"relativeEntities":1523,"slug":1524,"properties":1525,"entityType":190,"verifyStatus":191,"verifyTime":1536,"verifyNote":193,"languages":1537,"translateLanguages":20,"viewCount":21,"primaryUrl":1538,"fullTextUrl":20,"authors":1539,"publicationType":244,"publisherRelationship":1593,"citationCount":21,"citationInfo":1636,"publishDate":1638,"publishYear":1224,"citationAnalyzeStatus":19,"lastCitationAnalyze":1639,"indexDatabases":1640,"openAccess":20,"references":1641,"isForceReanalyzing":299},"64927107-f07b-4e64-8106-16ce4fd1b4ea","2024-04-15T13:15:32.240+00:00","2026-07-06T08:49:30.805+00:00",[],"Defining-and-Providing-Coverage-for-Assertion-Based-Dynamic-Verification",{"openalex":1526,"mag":1528,"title":1530,"gsPaper":1532,"doi":1534},{"VOID":1527},"W2013029218",{"VOID":1529},"2013029218",{"EN":1531},"Defining and Providing Coverage for Assertion-Based Dynamic Verification",{"VOID":1533},"[\"13269917748103681525\"]",{"VOID":1535},"10.1007\u002Fs10836-010-5148-9","2024-05-16T11:19:04.218+00:00",[1081],"http:\u002F\u002Flink.springer.com\u002F10.1007\u002Fs10836-010-5148-9",[1540,1559,1576],{"id":1541,"sortIndex":21,"researcher":20,"roles":1542,"affiliations":1543,"properties":1552,"displayName":1556,"givenName":20,"familyName":20},"f192727b-4333-4a65-af4d-0edd228e609c",[],[1544],{"id":1545,"sortIndex":21,"affiliation":1546,"properties":20},"256194d6-5252-4b2d-a086-8db3b7cb13f4",{"id":1545,"createTime":20,"updateTime":20,"relativeEntities":1547,"slug":20,"properties":1548,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1551,"statistic":20},[],{"title":1549},{"EN":1550},"Department of Electrical and Computer Engineering, Integrated Microsystems Laboratory, McGill University, Montréal, Canada",[],{"orcid":1553,"title":1555,"openalex":1557},{"VOID":1554},"https:\u002F\u002Forcid.org\u002F0009-0001-4468-3152",{"EN":1556},"Jason G. Tong",{"VOID":1558},"A5051076104",{"id":1560,"sortIndex":91,"researcher":20,"roles":1561,"affiliations":1562,"properties":1569,"displayName":1571,"givenName":20,"familyName":20},"6604f7b5-e132-4c2e-8011-3c31e72a6ea6",[],[1563],{"id":1545,"sortIndex":21,"affiliation":1564,"properties":20},{"id":1545,"createTime":20,"updateTime":20,"relativeEntities":1565,"slug":20,"properties":1566,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1568,"statistic":20},[],{"title":1567},{"EN":1550},[],{"title":1570,"gsAuthor":1572,"openalex":1574},{"EN":1571},"Marc Boulé",{"VOID":1573},"[\"y3ukjHkAAAAJ\"]",{"VOID":1575},"A5068027997",{"id":1577,"sortIndex":139,"researcher":20,"roles":1578,"affiliations":1579,"properties":1586,"displayName":1590,"givenName":20,"familyName":20},"c07ead78-fa8c-43e2-90f2-65a88ed169c0",[],[1580],{"id":1545,"sortIndex":21,"affiliation":1581,"properties":20},{"id":1545,"createTime":20,"updateTime":20,"relativeEntities":1582,"slug":20,"properties":1583,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1585,"statistic":20},[],{"title":1584},{"EN":1550},[],{"orcid":1587,"title":1589,"openalex":1591},{"VOID":1588},"https:\u002F\u002Forcid.org\u002F0000-0002-6887-3911",{"EN":1590},"Željko Žilić",{"VOID":1592},"A5062514163",{"url":20,"publisher":1594,"properties":20},{"id":6,"createTime":7,"updateTime":8,"relativeEntities":1595,"slug":10,"properties":1596,"entityType":18,"verifyStatus":19,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":21,"subjectFields":1600,"manageAffiliations":1605,"indexDatabases":1616,"url":20,"thumbnailPath":20,"statistic":1631,"gsStatistic":20,"type":20,"analyzePriority":20},[],{"issn":1597,"title":1598,"eissn":1599},{"VOID":13},{"EN":15},{"VOID":17},[1601],{"id":24,"createTime":20,"updateTime":20,"relativeEntities":1602,"label":1603,"description":1604,"parentId":20,"standard":20,"scholarHubFieldId":20},[],{"EN":27},{},[1606,1611],{"id":31,"createTime":20,"updateTime":20,"relativeEntities":1607,"slug":20,"properties":1608,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1610,"statistic":20},[],{"title":1609},{"EN":35},[37],{"id":39,"createTime":20,"updateTime":20,"relativeEntities":1612,"slug":20,"properties":1613,"entityType":20,"verifyStatus":20,"verifyTime":20,"verifyNote":20,"languages":20,"translateLanguages":20,"viewCount":20,"url":20,"parentIds":1615,"statistic":20},[],{"title":1614},{"EN":43},[],[1617,1624],{"id":47,"indexDatabase":1618,"url":58,"indexYears":59,"academicFieldIds":1623,"indexDatabaseRanking":62},{"id":49,"createTime":20,"updateTime":20,"relativeEntities":1619,"label":1620,"description":1621,"key":55,"publicationTags":1622,"standard":20},[],{"EN":52,"VI":52},{"EN":52,"VI":54},[57],[61],{"id":64,"indexDatabase":1625,"url":77,"indexYears":20,"academicFieldIds":1630,"indexDatabaseRanking":20},{"id":66,"createTime":20,"updateTime":20,"relativeEntities":1626,"label":1627,"description":1628,"key":73,"publicationTags":1629,"standard":20},[],{"EN":69,"VI":69},{"EN":71,"VI":72},[75,76],[79],{"impactFactor":21,"impactFactorByYear":1632,"i10Index":90,"i10IndexLast5Year":91,"totalPublication":92,"totalPublicationByYear":1633,"totalCitation":117,"totalCitationByYear":1634,"totalCitationPerPublication":140,"totalCitationPerPublicationByYear":1635,"hindexLast5Year":168,"hindex":168},{"2012":82,"2013":83,"2014":84,"2015":85,"2016":82,"2017":86,"2018":87,"2019":88,"2020":82,"2021":89,"2022":82,"2023":83},{"1990":94,"1991":95,"1992":96,"1993":97,"1994":96,"1995":98,"1996":99,"1997":100,"1998":98,"1999":101,"2000":102,"2001":103,"2002":104,"2003":105,"2004":106,"2005":107,"2006":102,"2007":105,"2008":106,"2009":108,"2010":109,"2011":107,"2012":110,"2013":111,"2014":107,"2015":112,"2016":113,"2017":105,"2018":114,"2019":90,"2020":107,"2021":106,"2022":114,"2023":115,"2024":116},{"1990":108,"1991":119,"1992":120,"1993":112,"1994":102,"1995":121,"1996":122,"2004":123,"2005":124,"2006":125,"2007":126,"2008":127,"2009":90,"2010":128,"2011":98,"2012":129,"2013":130,"2014":131,"2015":132,"2016":98,"2017":133,"2018":134,"2019":135,"2020":136,"2021":137,"2022":138,"2023":139},{"1990":142,"1991":143,"1992":144,"1993":145,"1994":146,"1995":147,"1996":148,"2004":146,"2005":149,"2006":150,"2007":151,"2008":152,"2009":153,"2010":154,"2011":155,"2012":156,"2013":157,"2014":158,"2015":159,"2016":160,"2017":161,"2018":162,"2019":163,"2020":164,"2021":165,"2022":166,"2023":167},{"total":21,"publishYear":1224,"statisticByYear":1637},{},"2010-04-01","2026-07-06T08:49:30.804+00:00",[62,75],[1642,1646,1649,1653,1657,1660,1664,1668,1672,1676,1680,1684,1687,1690,1694,1698,1701,1704,1708,1712,1715,1719,1723,1727,1731,1735,1739,1742,1745],{"id":20,"text":1643,"url":20,"identifiers":1644},"Ammann P, Offutt J (2008) Introduction to software testing. Cambridge University Press, New York",{"doi":1645},"10.1017\u002FCBO9780511809163",{"id":20,"text":1647,"url":20,"identifiers":1648},"Anderson TL (2005) Coverage is the heart of verification. EETimes. Available online: http:\u002F\u002Fwww.eetimes.com\u002Fnews\u002Fdesign\u002Ffeatures\u002FshowArticle.jhtml?articleID=60400630",{},{"id":20,"text":1650,"url":20,"identifiers":1651},"Ball T, Kupferman O (2008) Vacuity in testing. In: Test and proofs, ser. Lecture notes in computer science, vol 4966. Springer, Berlin, pp 4–17",{"doi":1652},"10.1007\u002F978-3-540-79124-9_2",{"id":20,"text":1654,"url":20,"identifiers":1655},"Beer I, Ben-David S, Eisner C, Rodeh Y (2001) Efficient detection of vacuity in temporal model checking. Form Methods Syst Des 18(2):141–163",{"doi":1656},"10.1023\u002FA:1008779610539",{"id":20,"text":1658,"url":20,"identifiers":1659},"Bening L, Foster H (2001) Principles of verifiable RTL design. Kluwer Academic, Norwell",{},{"id":20,"text":1661,"url":20,"identifiers":1662},"Boulé M, Chenard J, Zilic Z (2006) Adding debug enhancements to assertion checkers for hardware emulation and silicon debug. In: International conference on computer design, pp 294–299",{"doi":1663},"10.1109\u002FICCD.2006.4380831",{"id":20,"text":1665,"url":20,"identifiers":1666},"Boulé M, Chenard J, Zilic Z (2007) Assertion checkers in verification, silicon debug and in-field diagnosis. In: Proceedings of the IEEE international symposium on quality electronic design, pp 613–620",{"doi":1667},"10.1109\u002FISQED.2007.38",{"id":20,"text":1669,"url":20,"identifiers":1670},"Boulé M, Chenard J, Zilic Z (2007) Debug enhancements in assertion-checker generation. IET Comput Digit Tech 1(6):669–677",{"doi":1671},"10.1049\u002Fiet-cdt:20060209",{"id":20,"text":1673,"url":20,"identifiers":1674},"Boulé M, Zilic Z (2007) Efficient automata-based assertion-checker synthesis of SEREs for hardware emulation. In: ASP-DAC ’07: proceedings of the 2007 conference on Asia South Pacific design automation. IEEE Computer Society, Washington, DC, pp 324–329",{"doi":1675},"10.1109\u002FASPDAC.2007.358006",{"id":20,"text":1677,"url":20,"identifiers":1678},"Boulé M, Zilic Z (2008) Automata-based assertion-checker synthesis of PSL properties. ACM Transact Des Automat Electron Syst 13(1):1–21",{"doi":1679},"10.1145\u002F1297666.1297670",{"id":20,"text":1681,"url":20,"identifiers":1682},"Boulé M, Zilic Z (2008) Generating hardware assertion checkers: for hardware verification, emulation, post-fabrication debugging and on-line monitoring. Springer, Berlin",{"doi":1683},"10.1007\u002F978-1-4020-8586-4",{"id":20,"text":1685,"url":20,"identifiers":1686},"Brzozowski J (1962) Canonical regular expressions and minimal state graphs for definite events. Math Theory Automata 12:529–561",{},{"id":20,"text":1688,"url":20,"identifiers":1689},"Calamé J (2006) Specification-based test generation with TGV. Centrum voor Wiskunde en Informatica",{},{"id":20,"text":1691,"url":20,"identifiers":1692},"Chatterjee D, Bertacco V (2009) Activity-based refinement for abstraction-guided simulation. In: Proceedings of IEEE high-level design validation and test workshop, pp 146–153",{"doi":1693},"10.1109\u002FHLDVT.2009.5340163",{"id":20,"text":1695,"url":20,"identifiers":1696},"Cheng K, Krishnakumar A (1993) Automatic functional test generation using the extended finite state machine model. In: Proceedings of the 30th international conference on design automation. ACM, New York, pp 86–91",{"doi":1697},"10.1145\u002F157485.164585",{"id":20,"text":1699,"url":20,"identifiers":1700},"Eisner C, Fisman D (2006) A practical introduction to PSL (Series on integrated circuits and systems). Springer, New York",{},{"id":20,"text":1702,"url":20,"identifiers":1703},"Foster H (2009) Applied assertion-based verification: an industry perspective. Found Trends Electron Des Autom 3(1):1–95",{},{"id":20,"text":1705,"url":20,"identifiers":1706},"Foster H, Lacey D, Krolnik A (2003) Assertion-based design. Kluwer Academic, Norwell",{"doi":1707},"10.1007\u002F978-1-4419-9228-4",{"id":20,"text":1709,"url":20,"identifiers":1710},"Hierons RM, et al (2009) Using formal specifications to support testing. ACM Comput Surv 41(2):1–76",{"doi":1711},"10.1145\u002F1459352.1459354",{"id":20,"text":1713,"url":20,"identifiers":1714},"Hopcroft J, Motwani R, Ullman J (2000) Introduction to automata theory, languages, and computation, 2nd edn. Addison Wesley, Reading",{},{"id":20,"text":1716,"url":20,"identifiers":1717},"Koo H-M, Mishra P (2006) Test generation using SAT-based bounded model checking for validation of pipelined processors. In: GLSVLSI ’06: proceedings of the 16th ACM Great Lakes symposium on VLSI. ACM, New York,pp 362–365",{"doi":1718},"10.1145\u002F1127908.1127991",{"id":20,"text":1720,"url":20,"identifiers":1721},"Kupferman O, Vardi M (2003) Vacuity detection in temporal model checking. Int J Softw Tools Technol Transf 4(2):224–233",{"doi":1722},"10.1007\u002Fs100090100062",{"id":20,"text":1724,"url":20,"identifiers":1725},"Mathaikutty DA, Ahuja S, Dingankar A, Shukla S (2007) Model-driven test generation for system level validation. In: High-level design, validation, and test workshop, IEEE international, pp 83–90",{"doi":1726},"10.1109\u002FHLDVT.2007.4392792",{"id":20,"text":1728,"url":20,"identifiers":1729},"Oddos Y, Morin-Allory K, Borrione D, Boulé M, Zilic Z (2009) MYGEN: automata-based on-line test generator for assertion-based verification. In: GLSVLSI ’09: proceedings of the 19th ACM Great Lakes symposium on VLSI. ACM, New York, pp 75–80",{"doi":1730},"10.1145\u002F1531542.1531563",{"id":20,"text":1732,"url":20,"identifiers":1733},"Pal B, Banerjee A, Sinha A, Dasgupta P (2008) Accelerating assertion coverage with adaptive testbenches. IEEE Trans Comput-Aided Des Integr Circuits Syst 27(5):967–972",{"doi":1734},"10.1109\u002FTCAD.2008.917975",{"id":20,"text":1736,"url":20,"identifiers":1737},"Shimizu K, Dill DL (2002) Deriving a simulation input generator and a coverage metric from a formal specification. In: DAC ’02: proceedings of the 39th annual design automation conference. ACM, New York, pp 801–806",{"doi":1738},"10.1145\u002F513918.514118",{"id":20,"text":1740,"url":20,"identifiers":1741},"Sordoillet J, Davey S (2006) Integrated, comprehensive assertion-based coverage. EDA Tech Forum 3(1):22–25",{},{"id":20,"text":1743,"url":20,"identifiers":1744},"Vijayaraghavan S, Ramanathan M (2005) A practical guide for systemVerilog assertions. Springer, Berlin",{},{"id":20,"text":1746,"url":20,"identifiers":1747},"Yuan J, Pixley C, Aziz A (2006) Constraint-based verification. Springer, Berlin",{}]