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other provinces and regions in Vietnam and other country.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Address\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Headquarters of Can Tho Journal of Medicine and Pharmacy, located Scientific Research and International Cooperation Office: 179 Nguyen Van Cu Street, An Khanh Ward, Ninh Kieu District, Can Tho City, Vietnam.\u003C\u002Fspan>\u003C\u002Fp>","\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Ngày 16\u002F7\u002F2015, Tạp chí Y Dược học Cần Thơ được cấp chỉ số quốc tế: ISSN 2354-1210.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Từ tháng 4\u002F2016, Tạp chí đã được Hội đồng Giáo sư ngành Y đưa vào danh sách các tạp chí khoa học Y học được tính điểm công trình 0-0,5 điểm cho một bài báo đăng.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Năm 2020 Tạp chí Y Dược học Cần Thơ đã được phê duyệt vào danh mục của các Hội đồng Giáo sư ngành Dược học được tính điểm công trình 0-0,5 điểm cho một bài báo đăng.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Tạp chí Y Dược học Cần Thơ ra 12 số\u002Fnăm, 180-200 trang\u002Fsố.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Từ tháng 12\u002F2022 Tạp chí Y Dược học Cần Thơ là thành viên của hệ thống Crossref và từ tháng 01\u002F2023 tạp chí thực hiện bình duyệt online kín 2 chiều nhằm tăng tính minh bạch, tin cậy của các công trình nghiên cứu khoa học và đảm bảo tốt nhất chất lượng khoa học của bài viết.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Tôn chỉ, mục đích và phạm vi của tạp chí\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Tôn chỉ và mục đích hoạt động của tạp chí: xuất bản nhằm mục đích phổ biến kết quả từ các đề tài nghiên cứu khoa học; giao lưu trao đổi khoa học, chia sẻ kinh nghiệm, học tập, đồng thời cập nhật thông tin khoa học mới trong các lĩnh vực y, sinh, dược học trong và ngoài nước.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Phạm vi của tạp chí: Tạp chí xuất bản được chia thành 3 chuyên mục: (i) Bài báo nghiên cứu khoa học là kết quả công trình nghiên cứu khoa học có giá trị đã được triển khai nghiên cứu, (ii) Bài tổng quan y, sinh, dược học: phục vụ mục tiêu đào tạo liên tục trong lĩnh vực y, sinh, dược học; nhằm hệ thống hóa những kiến thức kinh điển và hiện đại; (iii) Thông tin cập nhật kiến thức mới về y, sinh, dược học trong nước và trên thế giới.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Chính sách truy cập mở\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Tạp chí Y Dược học Cần Thơ áp dụng chính sách truy cập mở đối với các bài báo đã xuất bản đến với độc giả, nhằm mở rộng cơ hội tiếp cận các kết quả nghiên cứu chất lượng cao và tăng cường trao đổi kiến thức. Tạp chí đăng tải trực tuyến (miễn phí) toàn văn các bài báo được công bố trên website của Tạp chí (https:\u002F\u002Ftapchi.ctump.edu.vn).\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Đạo đức xuất bản\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Tạp chí Y Dược học Cần Thơ cam kết tuân thủ đạo đức xuất bản phù hợp với các hướng dẫn và tiêu chuẩn của the Committee on Publication Ethics (COPE), tuân thủ các nguyên tắc của COPE’s Core Practices, Best Practices Guidelines for Journal Editors và Guidelines on Good Publication Practices.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Bản thảo bài báo chỉ được chấp nhận khi được tác giả chịu trách nhiệm chính cam kết các nội dung sau: Các nội dung của bản thảo chưa được đăng tải toàn bộ hoặc một phần ở các tạp chí khác; Tất cả các tác giả đều có đóng góp một cách đáng kể vào quá trình nghiên cứu hoặc chuẩn bị bản thảo và cùng chịu trách nhiệm về các nội dung của bản thảo; Tuân thủ các biện pháp đảm bảo đạo đức nghiên cứu (ví dụ thỏa thuận đồng ý tham gia nghiên cứu).\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Cam kết bảo mật\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Tạp chí cam kết thực hiện và tuân thủ các quy định của luật và các văn bản hướng dẫn liên quan đến bảo mật thông tin cá nhân trên không gian mạng. Các thông tin mà người dùng (tác giả, độc giả, biên tập viên, người phản biện) nhập vào các biểu mẫu trên Hệ thống Quản lý xuất bản trực tuyến của tạp chí chỉ được sử dụng vào các mục đích đã được tuyên bố rõ ràng và sẽ không được cung cấp cho bất kỳ bên thứ ba nào khác, hay dùng vào bất kỳ mục đích nào khác.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Phí gửi bài\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Lệ phí gửi đăng bài: 1.000.000đ\u002Fbài báo\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Lệ phí gửi đăng nhanh: 1.500.000đ\u002Fbài báo\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Đối với tác giả là cán bộ viên chức thuộc Trường Đại học Y Dược Cần Thơ thì được hỗ trợ 50% lệ phí gửi đăng bài.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Đối với sinh viên thực hiện đề tài nghiên cứu khoa học cấp trường được hỗ trợ 100% lệ phí đăng bài ( Tác giả gửi đính kèm “ Quyết định về việc giao tổ chức thực hiện đề tài nghiên cứu khoa học cấp Trường của sinh viên”).\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Hình thức nộp lệ phí:\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">1. Tiền mặt:\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Nộp trực tiếp tại Phòng Tài chính - Kế toán, Trường Đại học Y Dược Cần Thơ, số 179 Nguyễn Văn Cừ, P. An Khánh, Q. Ninh Kiều, thành phố Cần Thơ.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">2. Chuyển khoản:\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Tên Tài khoản: Trường ĐHYD Cần Thơ, Số TK: 0111000115668, tại ngân hàng Vietcombank chi nhánh Cần Thơ.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Thời gian: Áp dụng từ ngày 01\u002F02\u002F2023.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">* Phí gửi bài không được hoàn trả khi bài viết bị từ chối hoặc tác giả xin rút bài viết.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Quy trình phản biện bài báo\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Tạp chí Y Dược học Cần Thơ thực hiện quy trình phản biện kín hai chiều nghiêm ngặt. Danh tính của những người phản biện không được tiết lộ cho các tác giả và ngược lại. Quy trình thẩm định bài báo đăng gồm các bước sau:\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Tiếp nhận bản thảo\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Tác giả liên hệ gửi bản thảo đến Tạp chí qua hệ thống trực tuyến tại website: https:\u002F\u002Ftapchi.ctump.edu.vn. Hướng dẫn về cách đăng ký, gửi bài và chuẩn bị bản thảo được cung cấp trên website của Tạp chí.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Sàng lọc sơ bộ\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Sau khi Tòa soạn nhận được bài báo của tác giả, Ban Thư ký sẽ tiến hành kiểm tra sơ bộ bài báo (các yêu cầu về nội dung và hình thức). Những bài báo không đúng quy cách hoặc có nội dung không phù hợp hoặc vi phạm bản quyền sẽ bị từ chối (Ban Thư ký thông báo phản hồi đến tác giả trong vòng 1 tuần). Những bài báo đủ điều kiện, được Ban Thư ký tòa soạn chuyển đến Ban Biên tập có cùng chuyên môn với nội dung bài báo để đề xuất người phản biện. Thời gian kể từ khi Ban Biên tập nhận bài báo đến khi đề xuất người phản biện bài báo chậm nhất là 5 ngày.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Vòng phản biện\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">1. Ban Thư ký gửi bài và yêu cầu phản biện đến 02 phản biện độc lập.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">2. Các phản biện gởi nhận xét cho Ban Thư ký. Thời gian từ khi gửi bài cho phản biện đến khi nhận ý kiến của phản biện tối đa là 20 ngày.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Xử ký kết quả phản biện\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">1. Nếu ý kiến đồng ý cho đăng và không cần chỉnh sửa, Ban Thư ký tiếp tục đăng bài theo qui trình.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">2. Nếu ý kiến đồng ý đăng và cần chỉnh sửa, Ban Thư ký sẽ thông tin đến tác giả chỉnh sửa theo yêu cầu của người phản biện. Thời gian chỉnh sửa và gửi lại kéo dài không quá 2 tuần, từ khi tác giả bài báo nhận được thông tin (Quá trình này có thể lặp lại tối đa 2 lần\u002F1 bài báo). Khi có sự thống nhất, đồng ý của người phản biện; bài báo được tiếp tục đăng theo qui trình.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">3. Những bài báo có chất lượng không đạt yêu cầu, cả 2 phản biện không đồng ý cho đăng sẽ bị Tòa soạn từ chối đăng.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">Xuất bản\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">1. Ban Thư ký tổng hợp các bản thảo đã được tác giả hoàn thiện sau thẩm định trình Ban Biên tập xem xét, Tổng Biên tập phê duyệt, quyết định bài đăng theo các tiêu chí: sự phù hợp nội dung với tôn chỉ và mục đích, thể loại bài viết (ưu tiên các bài có bài có nghiên cứu chuyên sâu, hàm lượng khoa học cao), đóng góp mới bài báo, bài báo được ưu tiên đăng trong số gần nhất của Tạp chí theo thứ tự: tính thời sự, chất lượng bài báo và thời gian gửi bài.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">2. Ban Biên tập và Ban Thư ký biên tập bản thảo, chế bản, đọc rà soát lỗi. Thời gian hoàn thành từ 10-15 ngày.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">3. Ban Thư ký có trách nhiệm thông báo cho tác giả bài báo (bằng e-mail) về tình hình phê duyệt bài báo, thời gian, số kỳ, tập xuất bản bài báo theo qui định.\u003C\u002Fspan>\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>\u003Cspan style=\"color: rgb(0, 0, 0);\">4. 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And the first issue was published in January 1998 with ISSN 1859-0128. Since then, STDJ has become the most important scientific forum of scientists from VNU-HCM as well as other universities. The magazine has undergone 20 years of development and has become a bridge for scientific exchanges, as well as enriching reference materials for the faculty, doctoral students, students of VNU-HCM in particular and other universities, institutes...\"},{\"attributes\":{\"align\":\"justify\"},\"insert\":\"\\n\"},{\"insert\":\"Science and Technology Development Journal - Health Sciences (STDJ-HS) is a subjournal of Science and Technology Development Journal since 2020.\"},{\"attributes\":{\"align\":\"justify\"},\"insert\":\"\\n\"},{\"insert\":\" \"},{\"attributes\":{\"align\":\"justify\"},\"insert\":\"\\n\"},{\"attributes\":{\"bold\":true},\"insert\":\"2. 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Landolt, “An analog CMOS implementation of a Kohonen network with learning capability,”3rd Int. Workshop on VLSI for Neural Networks and Artificial Intelligence, Oxford, 1992.",{},{"id":26,"text":1498,"url":26,"identifiers":1499},"M. Lenzlinger and E. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,”J. Appl. Phys., Vol. 40, p. 278, 1969.",{"doi":1500},"10.1063\u002F1.1657043",{"id":26,"text":1502,"url":26,"identifiers":1503},"E. Säckinger and W. Guggenbühl, “An analog trimming circuit based on a floating-gate device,”IEEE J. Solid-State Circuits, Vol. SC-23, No. 6, pp. 1437–1440, 1988.",{"doi":1504},"10.1109\u002F4.90044",{"id":26,"text":1506,"url":26,"identifiers":1507},"M. Holler et al., “An electrically trainable artificial neural network (ETANN) with 10240 floating gate synapses,” inProc. Int. Joint Conf. on Neural Networks, Washington, pp. II-191–II-196, 1989.",{"doi":1508},"10.1109\u002FIJCNN.1989.118698",{"id":26,"text":1510,"url":26,"identifiers":1511},"B. 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Although low power hardware components are critical for reducing energy consumption, the switching activity, which is the main source of dynamic power dissipation in electronic systems, is largely determined by the software running on these systems. In this paper, we present and evaluate several instruction scheduling algorithms that reorder a given sequence of instructions taking into account the energy considerations. We first compare a performance-oriented scheduling technique with three energy-oriented instruction scheduling algorithms from both performance (execution cycles of the resulting schedules) and energy consumption points of view. Then, we propose three scheduling algorithms that consider energy and performance at the same time. Our experimentation with these scheduling techniques shows that the best scheduling from the performance perspective is not necessarily the best scheduling from the energy perspective. Further, scheduling techniques that consider both energy and performance simultaneously are found to be desirable, that is, these techniques are quite successful in reducing energy consumption and their performance (in terms of execution cycles) is comparable to that of a pure performance-oriented scheduling. We also illuminate the inherent approximations and difficulties in building energy models for enabling energy-aware instruction scheduling and explore alternative options using cycle-accurate energy simulator. The simulation results show that the energy-oriented scheduling reduces energy consumption by up to 30% compared to the performance-oriented scheduling.","Giảm tiêu thụ năng lượng đã trở thành một vấn đề quan trọng trong thiết kế hệ thống phần cứng và phần mềm trong những năm gần đây. Mặc dù các thành phần phần cứng tiêu thụ điện năng thấp là rất cần thiết để giảm tiêu thụ năng lượng, nhưng hoạt động chuyển đổi, là nguồn chính gây tiêu tán điện năng động trong các hệ thống điện tử, chủ yếu được xác định bởi phần mềm chạy trên các hệ thống này. Trong bài báo này, chúng tôi trình bày và đánh giá một số thuật toán lập lịch hướng dẫn mà sắp xếp lại một chuỗi lệnh nhất định với sự xem xét đến các yếu tố năng lượng. Chúng tôi đầu tiên so sánh một kỹ thuật lập lịch hướng tới hiệu suất với ba thuật toán lập lịch hướng tới năng lượng từ cả quan điểm hiệu suất (chu kỳ thực thi của các lịch trình tạo ra) và tiêu thụ năng lượng. Sau đó, chúng tôi đề xuất ba thuật toán lập lịch mà xem xét đến năng lượng và hiệu suất cùng một lúc. Các thí nghiệm của chúng tôi với các kỹ thuật lập lịch này cho thấy rằng lập lịch tốt nhất từ quan điểm hiệu suất không nhất thiết là lập lịch tốt nhất từ quan điểm năng lượng. Thêm vào đó, các kỹ thuật lập lịch xem xét cả năng lượng và hiệu suất đồng thời được tìm thấy là mong muốn, nghĩa là, các kỹ thuật này khá thành công trong việc giảm tiêu thụ năng lượng và hiệu suất của chúng (theo chu kỳ thực thi) có thể so sánh được với một lịch trình thuần túy hướng tới hiệu suất. Chúng tôi cũng làm rõ các xấp xỉ và khó khăn vốn có trong việc xây dựng các mô hình năng lượng để cho phép lập lịch hướng tới năng lượng và khám phá các tùy chọn thay thế sử dụng trình giả lập năng lượng chính xác theo chu kỳ. Kết quả mô phỏng cho thấy lập lịch hướng tới năng lượng giảm tiêu thụ năng lượng lên đến 30% so với lập lịch hướng tới hiệu suất.",{"EN":2084,"VI":2085},"Instruction Scheduling for Low Power","Lập Lịch Hướng Dẫn cho Hiệu Năng Thấp",{"VOID":2087},"10.1023\u002FB:VLSI.0000017007.28247.f6",{"VOID":2089},"16732257880704027674",{"VI":2091},"tiêu thụ năng lượng, lập lịch hướng dẫn, phần cứng, phần mềm, hiệu suất, mô hình năng lượng","2024-04-29T01:27:29.781+00:00",[101],"https:\u002F\u002Flink.springer.com\u002Farticle\u002F10.1023\u002FB:VLSI.0000017007.28247.f6",[2096,2117,2132,2145,2158],{"id":2097,"sortIndex":114,"researcher":26,"roles":2098,"affiliations":2100,"properties":2112},"96d158da-9bcc-4eab-9196-575b7c9f53e8",[2099],"AUTHOR",[2101],{"id":2102,"sortIndex":36,"affiliation":2103,"properties":26},"5a5a185b-daad-49a0-b380-74202b1d22cd",{"id":2104,"createTime":2105,"updateTime":2106,"relativeEntities":2107,"slug":2108,"properties":2109,"entityType":98,"verifyStatus":28,"verifyTime":26,"verifyNote":26,"syncStatus":28,"languages":26,"translateLanguages":26,"viewCount":36},"c0549c57-3219-4f70-895b-8defb299e38a","2024-01-12T17:46:30.623+00:00","2024-10-07T08:32:06.858+00:00",[],"Department-of-Computer-Science-and-Engineering-The-Pennsylvania-State-University-University-Park-USA",{"title":2110},{"VI":2111},"Department of Computer Science and Engineering, The Pennsylvania State University, University Park, USA",{"title":2113,"gsAuthor":2115},{"VI":2114},"M. Kandemir",{"VOID":2116},"j67v24EAAAAJ",{"id":2118,"sortIndex":59,"researcher":26,"roles":2119,"affiliations":2120,"properties":2127},"fbcd6b75-6d68-4abf-aab9-0a7be4f92284",[2099],[2121],{"id":2122,"sortIndex":36,"affiliation":2123,"properties":26},"999b9d1c-5727-4b84-84b1-83cafe296a53",{"id":2104,"createTime":2105,"updateTime":2106,"relativeEntities":2124,"slug":2108,"properties":2125,"entityType":98,"verifyStatus":28,"verifyTime":26,"verifyNote":26,"syncStatus":28,"languages":26,"translateLanguages":26,"viewCount":36},[],{"title":2126},{"VI":2111},{"title":2128,"gsAuthor":2130},{"VI":2129},"N. Vijaykrishnan",{"VOID":2131},"UyeTBeoAAAAJ",{"id":2133,"sortIndex":36,"researcher":26,"roles":2134,"affiliations":2135,"properties":2142},"3dc33e16-9e10-43cc-a0b9-d8d83881fd6f",[2099],[2136],{"id":2137,"sortIndex":36,"affiliation":2138,"properties":26},"e9427f03-0257-40b8-8964-6cc78e9f2799",{"id":2104,"createTime":2105,"updateTime":2106,"relativeEntities":2139,"slug":2108,"properties":2140,"entityType":98,"verifyStatus":28,"verifyTime":26,"verifyNote":26,"syncStatus":28,"languages":26,"translateLanguages":26,"viewCount":36},[],{"title":2141},{"VI":2111},{"title":2143},{"VI":2144},"A. Parikh",{"id":2146,"sortIndex":115,"researcher":26,"roles":2147,"affiliations":2148,"properties":2155},"f3cd1377-b22b-4e1a-9a22-db5f4d5a1e12",[2099],[2149],{"id":2150,"sortIndex":36,"affiliation":2151,"properties":26},"8d1fa03c-0970-4ed8-973f-95c2aa11a684",{"id":2104,"createTime":2105,"updateTime":2106,"relativeEntities":2152,"slug":2108,"properties":2153,"entityType":98,"verifyStatus":28,"verifyTime":26,"verifyNote":26,"syncStatus":28,"languages":26,"translateLanguages":26,"viewCount":36},[],{"title":2154},{"VI":2111},{"title":2156},{"VI":2157},"Soontae Kim",{"id":2159,"sortIndex":111,"researcher":26,"roles":2160,"affiliations":2161,"properties":2168},"f0eb684c-aa74-4928-b7a3-d72989e77a48",[2099],[2162],{"id":2163,"sortIndex":36,"affiliation":2164,"properties":26},"82bfce1d-b739-4df0-98dc-f944aff48c3b",{"id":2104,"createTime":2105,"updateTime":2106,"relativeEntities":2165,"slug":2108,"properties":2166,"entityType":98,"verifyStatus":28,"verifyTime":26,"verifyNote":26,"syncStatus":28,"languages":26,"translateLanguages":26,"viewCount":36},[],{"title":2167},{"VI":2111},{"title":2169},{"VI":2170},"M.J. Irwin",{"url":2094,"publisher":2172,"properties":2185},{"id":659,"createTime":660,"updateTime":661,"relativeEntities":2173,"slug":663,"properties":2174,"entityType":24,"verifyStatus":28,"verifyTime":26,"verifyNote":26,"syncStatus":28,"languages":26,"translateLanguages":26,"viewCount":36,"subjectFields":2177,"manageAffiliations":2178,"indexDatabases":2179,"url":672,"thumbnailPath":26,"statistic":2180,"gsStatistic":26,"type":175,"analyzePriority":26},[],{"issn":2175,"title":2176},{"VOID":666},{"EN":668},[],[],[],{"impactFactor":36,"impactFactorByYear":2181,"i10Index":239,"i10IndexLast5Year":36,"totalPublication":675,"totalPublicationByYear":2182,"totalCitation":677,"totalCitationByYear":2183,"totalCitationPerPublication":682,"totalCitationPerPublicationByYear":2184,"hindexLast5Year":298,"hindex":298},{},{"1989":59,"1990":111,"1991":162,"1992":162,"1993":53,"1994":50,"1995":111,"1996":111,"1997":50,"1998":103,"1999":52,"2000":158,"2001":116,"2002":50,"2003":52,"2004":103,"2005":103,"2006":50},{"1989":234,"1990":298,"1991":652,"1992":517,"1993":679,"1994":680,"1995":249,"1996":516,"2004":566,"2005":681,"2006":242},{"1989":684,"1990":371,"1991":685,"1992":686,"1993":687,"1994":688,"1995":336,"1996":689,"2004":690,"2005":691,"2006":692},{"volume":2186,"pages":2188},{"VOID":2187},"37",{"VOID":2189},"129-149",{"total":250,"publishYear":2071,"statisticByYear":2191},{"2004":114,"2005":111,"2006":59,"2007":59,"2008":111,"2009":162,"2010":162,"2011":162,"2012":116,"2013":135,"2014":111,"2015":59,"2016":158,"2018":114,"2020":115,"2023":115},[2193,2199,2202,2205,2208,2211,2214,2217,2220,2223,2226,2229,2232,2235,2238,2241,2244,2247,2250,2256,2259,2262,2265,2268,2271,2274,2277,2280,2283,2286,2289,2292,2295,2298,2301,2308,2311,2314,2317,2320,2323,2330,2333,2336,2339,2342,2345,2348,2351],{"id":2194,"text":2195,"url":2196,"identifiers":2197},"4c68646b-0035-4279-8000-0006b275d4fa","J.R. Lorch and A.J. Smith, “Software Strategies for Portable Computer Energy Management,” IEEE Personal Communications, June 1998, pp. 60-73.","https:\u002F\u002Flink.springer.com\u002F10.1007\u002Fs10440-022-00541-7",{"doi":2198},"10.1007\u002Fs10440-022-00541-7",{"id":26,"text":2200,"url":26,"identifiers":2201},"A. Chandrakasan and R. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995.",{},{"id":26,"text":2203,"url":26,"identifiers":2204},"G. Albera and R.I. Bahar, “Power and Performance Tradeoffs Using Various Cache Configurations,” in Proc. Power Driven Micro-Architecture Workshop, in conjunction with ISCA'98, Barcelona, Spain, June 1998.",{},{"id":26,"text":2206,"url":26,"identifiers":2207},"C.-L. Su and A.M. Despain, “Cache Design Trade-Offs for Power and Performance Optimization: A Case Study,” in Proc. International Symposium on Low Power Electronics and Design, 1995, pp. 63-68.",{},{"id":26,"text":2209,"url":26,"identifiers":2210},"B. Burgress et al., “The PowerPCTM603 Microprocessor: A High-Performance, Low-Power, Super-Scalar RISC Processor,” in Proc. IEEE COMPCON, Feb. 1994.",{},{"id":2194,"text":2212,"url":2196,"identifiers":2213},"S.B. Furber et al., “AMULET1: A Micro-Pipelined ARM,” in Proc. IEEE COMPCON, Feb. 1994.",{"doi":2198},{"id":2194,"text":2215,"url":2196,"identifiers":2216},"S. Manne, A. Klauser, and D. Grunwald, “Pipeline Gating: Speculation Control for Energy Reduction,” in Proc. 1998 Intl. Symposium on Computer Architecture, Barcelona, Spain, June 1998.",{"doi":2198},{"id":2194,"text":2218,"url":2196,"identifiers":2219},"K. Roy and M.C. Johnson, “Software Design for Low Power,” in Low Power Design in Deep Sub-micron Electronics, J. Mermet and W. Nebel (Eds.), Kluwer Academic Press, October 1996, pp. 433-459.",{"doi":2198},{"id":2194,"text":2221,"url":2196,"identifiers":2222},"F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. DeMan, “Global Communication and Memory Optimizing Transformations for Low Power Signal Processing Systems,” in Proc. IEEE Workshop on VLSI Signal Processing, 1994, pp. 178-187.",{"doi":2198},{"id":26,"text":2224,"url":26,"identifiers":2225},"F. Catthoor, S. Wuytack, E.D. Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle, Custom Memory Management Methodology—Exploration of Memory Organization for Embedded Multimedia System Design, Kluwer Academic Publishers, June, 1998.",{},{"id":2194,"text":2227,"url":2196,"identifiers":2228},"J.T. Russell and M.F. Jacome, “Software Power Estimation and Optimization for High Performance, 32 Bit Embedded Processors,” in Proc. ICCD'98, Austin, TX, Oct. 1998.",{"doi":2198},{"id":2194,"text":2230,"url":2196,"identifiers":2231},"C.-L. Su, C.-Y. Tsui, and A.M. Despain, “Low Power Architecture Design and Compilation Techniques for High-Performance Processors,” in Proc. IEEE COMCON, 1994, pp. 489-498.",{"doi":2198},{"id":26,"text":2233,"url":26,"identifiers":2234},"M.C. Toburen, T.M. Conte, and M. Reilly, “Instruction Scheduling for Low Power Dissipation in High Performance Processors,” in Proc. Power Driven Micro-Architecture Workshop in Conjunction with the ISCA'98. Barcelona, Spain, June 1998.",{},{"id":26,"text":2236,"url":26,"identifiers":2237},"M. Lee, V. Tiwari, S. Malik, and M. Fujita, “Power Analysis and Minimization Techniques for Embedded DSP Software,” Fujitsu Scientific and Technical Journal, vol. 31, no. 2, 1995, pp. 215-229.",{},{"id":2194,"text":2239,"url":2196,"identifiers":2240},"V. Tiwari, S. Malik, A. Wolfe, and T.C. Lee, “Instruction Level Power Analysis and Optimization of Software,” Journal of VLSI Signal Processing Systems, vol. 13, no. 2, 1996.",{"doi":2198},{"id":2194,"text":2242,"url":2196,"identifiers":2243},"V. Tiwari, S. Malik, and A. Wolfe, “Power Analysis of Embedded Software: A First Step Towards Software Power Minimization,” IEEE Transactions on VLSI Systems, Dec. 1994.",{"doi":2198},{"id":2194,"text":2245,"url":2196,"identifiers":2246},"S. Coleman and K. McKinley, “Tile Size Selection Using Cache Organization and Data Layout,” in Proc. SIGPLAN '95 Conference on Programming Language Design and Implementation, June 1995.",{"doi":2198},{"id":2194,"text":2248,"url":2196,"identifiers":2249},"M. Wolf and M. Lam, “A Data Locality Optimizing Algorithm,” in Proc. ACM SIGPLAN 91 Conf. on Programming Language Design and Implementation, June 1991, pp. 30-44.",{"doi":2198},{"id":2251,"text":2252,"url":2253,"identifiers":2254},"a170d3b7-90df-4525-8db3-ee15e70f6ddf","M. Wolf, D. Maydan, and D. Chen, “Combining Loop Transformations Considering Caches and Scheduling,” in Proc. MICRO-29, Paris, France, Dec. 1996, pp. 274-286.","http:\u002F\u002Flink.springer.com\u002F10.1023\u002FA:1018754616274",{"doi":2255},"10.1023\u002FA:1018754616274",{"id":2194,"text":2257,"url":2196,"identifiers":2258},"M. Kandemir, J. Ramanujam, and A. Choudhary, “Improving Cache Locality by a Combination of Loop and Data Transformations,” IEEE Transactions on Computers, vol. 48, no. 2, 1999, pp. 159-167.",{"doi":2198},{"id":2194,"text":2260,"url":2196,"identifiers":2261},"M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, and J. Ramanujam, “A Linear Algebra Framework for Automatic Determination of Optimal Data Layouts,” IEEE Transactions on Parallel and Distributed Systems, vol. 10, no. 2, 1999, pp. 115-135.",{"doi":2198},{"id":2194,"text":2263,"url":2196,"identifiers":2264},"K. Ebcioglu, R.D. Groves, K.-C. Kim, G.M. Silberman, and I. Ziv, “VLIW Compilation Techniques in a Superscalar Environment,” in Proc. the ACM SIGPLAN'94 Conference on Programming Language Design and Implementation, Orlando, Florida, 20–24 June 1994, pp. 36-48.",{"doi":2198},{"id":2194,"text":2266,"url":2196,"identifiers":2267},"A. Chandrakasan et al., “Optimizing Power Using Transformations,” IEEE Trans. on CAD, vol. TCAD-14, no. 1, 1995, pp. 12-31.",{"doi":2198},{"id":2194,"text":2269,"url":2196,"identifiers":2270},"T. Sato, Y. Ootaguro, M. Nagamatsu, and H. Tago, “Evaluation of Architecture-Level Power Estimation for CMOS RISC Processors,” in Proc. the Symposium on Low Power Electronics, 1995, pp. 44-45.",{"doi":2198},{"id":26,"text":2272,"url":26,"identifiers":2273},"H.A. Mehta, System Level Power Analysis. Ph.D. Thesis, CSE Department, The Pennsylvania State University, State College, PA, Dec. 1996.",{},{"id":2194,"text":2275,"url":2196,"identifiers":2276},"H. Mehta, M.J. Irwin, and R.M. Owens, “Energy Characterization Based on Clustering,” in Proc. of the 33rd Design Automation Conference, June 1996, p. 702.",{"doi":2198},{"id":26,"text":2278,"url":26,"identifiers":2279},"J. Bunda, W.C. Athas, and D. Fussell, “Evaluating Power Implication of CMOS Microprocessor Design Decisions,” in Proc. the 1994 International Workshop on Low Power Design, April 1994.",{},{"id":26,"text":2281,"url":26,"identifiers":2282},"J.W. Davidson and S. Jinturkar, “Memory Access Coalescing: A Technique for Eliminating Redundant Memory Accesses,” ACM SIGPLAN Notices, vol. 29, no. 6, 1994.",{},{"id":2194,"text":2284,"url":2196,"identifiers":2285},"A. Sudarsanam and S. Malik, “Memory Bank and Register Allocation in Software Synthesis for ASIPs,” in Proc. the International Conference on Computer-Aided Design, 1995, pp. 388-392.",{"doi":2198},{"id":2194,"text":2287,"url":2196,"identifiers":2288},"E. DeGreef, F. Catthoor, and H. DeMan, “Memory Organization for Video Algorithms on Programmable Signal Processors,” in Proc. the IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1995, pp. 552-557.",{"doi":2198},{"id":2194,"text":2290,"url":2196,"identifiers":2291},"P.R. Panda, N.D. Dutt, and A. Nicolau, “Architectural Exploration and Optimization of Local Memory in Embedded Systems,” in Proc. ISSS'97, Antwerp, Sept. 1997.",{"doi":2198},{"id":2194,"text":2293,"url":2196,"identifiers":2294},"W.-T. Shiue and C. Chakrabarti, “Memory Exploration for Low Power, Embedded Systems,” in Proc. DAC'99, New Orleans, Louisiana, 1999.",{"doi":2198},{"id":2194,"text":2296,"url":2196,"identifiers":2297},"A. Parikh, M. Kandemir, N. Vijaykrishnan, and M.J. Irwin, “Instruction Scheduling Based on Energy and Performance Constraints,” in Proc. IEEE CS Annual Workshop on VLSI, April 2000.",{"doi":2198},{"id":2194,"text":2299,"url":2196,"identifiers":2300},"A. Parikh, M. Kandemir, N. Vijaykrishnan, and M.J. Irwin, “Energy Aware Instruction Scheduling,” in Proc. International Conference on High Performance Computing, Dec. 2000.",{"doi":2198},{"id":2302,"text":2303,"url":2304,"identifiers":2305},"58302f7c-0b24-496d-b2a6-4c0f466315e0","S.S. Muchnick, Advanced Compiler Design Implementation. San Francisco, California: Morgan Kaufmann Publishers, 1997.","https:\u002F\u002Fwww.goodreads.com\u002Fbook\u002Fshow\u002F887908.Advanced_Compiler_Design_and_Implementation",{"isbn":2306,"isbn13":2307},"1558603204","9781558603202",{"id":2194,"text":2309,"url":2196,"identifiers":2310},"M.S. Lam, “Software Pipelining: An Efficient Scheduling Techniques for VLIW Machines,” in Proc. ACM SIGPLAN 88 Conf. on Programming Language Design and Implementation, June 1988, pp. 318-328.",{"doi":2198},{"id":2194,"text":2312,"url":2196,"identifiers":2313},"M. Smotherman, S. Krishnamurthy, P.S. Aravind, and D. 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