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Mag., 37, 42, 10.1109\u002FMC.2004.1274003\nSotiriadis, 2003, Energy reduction in VLSI computation modules: an information-theoretic approach, IEEE Trans. Inf. Theory, 49, 790, 10.1109\u002FTIT.2003.809601\nXie, 2013, Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes, Integr. VLSI J., on-line\nSerafy, 2013, A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs, Integr. VLSI J., on-line\nWang, 2013, Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs, Integr. VLSI J., on-line\nMesgarzadeh, 2013, Simultaneous switching noise reduction by resonant clock distribution networks, Integr. VLSI J., on-line\nMazreah, 2013, Low-leakage soft error tolerant port-less configuration memory cells for FPGAs, Integr. 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VLSI Syst., 8, 379, 10.1109\u002F92.863617\nBrusamarello, 2008, Probabilistic approach for yield analysis of dynamic logic circuits, IEEE Trans. Circuits Syst. Regul. Pap., 55, 2238, 10.1109\u002FTCSI.2008.918141\nKorkmaz, 2008, Energy, performance, and probability tradeoffs for energy-efficient probabilistic CMOS circuits, IEEE Trans. Circuits Syst. Regul. Pap., 55, 2249, 10.1109\u002FTCSI.2008.920139\nC. Lin, H. Zhou, Trade-off between latch and flop for min-period sequential circuit designs with crosstalk, in: Proceeding of International Conferences on Computer-Aided Design, pp. 329–334, 2005.\nS. Lin, Y.B. Kim, F. Lombardi, Soft error hardening designs of nanoscale CMOS latches, in: Proceeding of IEEE VLSI Test Symposium, pp. 41-46, May 2009.\nFazeli, 2009, Low energy single event upset\u002Fsingle event transient-tolerant latch for deep sub-micron technologies, IET Comput. Digital Tech., 3, 289, 10.1049\u002Fiet-cdt.2008.0099\nOmana, 2010, High-performance robust latches, IEEE Trans. Comput., 59, 1455, 10.1109\u002FTC.2010.24\nIbe, 2010, Impact of scaling on neutron-induced soft error in SRAMs from a 250nm to a 22nm design rule, IEEE Trans. Electron Devices, 57, 1527, 10.1109\u002FTED.2010.2047907\nOmana, 2007, Latch susceptibility to transient faults and new hardening approach, IEEE Trans. Comput., 56, 1255, 10.1109\u002FTC.2007.1070\nPfau, 2010, Phase-noise-tolerant two-stage carrier recovery concept for higher order QAM formats, IEEE J. Sel. Top Quantum Electron., 16, 1210, 10.1109\u002FJSTQE.2009.2034472\nYamaguchi, 2009, A 2.0Gb\u002Fs clock-embedded interface for full-HD 10-bit 120Hz LCD drivers with 1\u002F5-rate noise-tolerant phase and frequency recovery, IEEE J. Solid-State Circuits, 44, 3560, 10.1109\u002FJSSC.2009.2031024\nFrustaci, 2008, High-performance noise-tolerant circuit techniques for CMOS dynamic logic, IET Circuits Devices Syst., 2, 537, 10.1049\u002Fiet-cds:20080070\nWey, 2008, Design and analysis of isolated noise-tolerant (INT) technique in dynamic CMOS circuits, IEEE Trans. Very Large Scale Integr. VLSI Syst., 16, 1708, 10.1109\u002FTVLSI.2008.2001563\nI.C. Wey, Y.G. Chen, C.H. Yu, J. Chen, A.Y. Wu, A 0.18μm probabilistic-based noise-tolerate circuit design and implementation with 28.7dB noise-immunity improvement, in: Proceeding of IEEE Asian Solid-State Circuits Conferences, pp. 291–294, Nov. 2006.\nWey, 2009, Design and implementation of cost-effective probabilistic-based noise tolerant VLSI circuits, IEEE Trans. Circuits Syst. Regul. Pap., 56, 2411, 10.1109\u002FTCSI.2009.2015648\nI.C. Wey, Y.G. Chen, C.H. Yu, J. Chen, A.Y. Wu, A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement, in: Proceeding of IEEE Asian Solid-State Circuits Conferences, pp. 316–319, Nov. 2007.\nK. Nepal, R.I. Bahar, J. Mundy, W.R. Patterson, A. Zaslavsky, Optimizing noise immune nanoscale circuits using principles of Markov random fields, in: Proceedings of Great Lakes Symposium on VLSI, April 2006, pp. 149-152.\nK. Nepal, R.I. Bahar, J. Mundy, W.R. Patterson, A. Zaslavsky, Techniques for designing noise-tolerant multi-level combinational circuits, in: Proceedings of Design, Automation and Test in Europe, March 2007, pp.576-581.\nR.I. Bahar, J. Chen, J. Mundy, A probabilistic-based design methodology for nanoscale computation, in: Proceeding of International Conferences on Computer Aided Design, pp. 480–486, 2003.\nK. Nepal, R.I. Bahar, J. Mundy, W.R. Patterson, A. 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Lackey, P.S. Zuchowski, T.R. Bednar, D.W. Stout, S.W. Gould, J.M. Cohn, Managing power and performance for system-on-chip designs using voltage islands, in: IEEE\u002FACM International Conference on Computer Aided Design, 2002, pp. 195–202.\nChang, 1997, Energy minimization using multiple supply voltages, IEEE Trans. Very Large Scale Integr. (VLSI) Syst, 5, 436, 10.1109\u002F92.645070\nW.-P. Lee, H.-Y. Liu, Y.-W. Chang, An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning, in: IEEE\u002FACM International Conference on Computer Aided Design, 2007, pp. 650–655.\nQ. Zaichen, E.F. Young, Multi-voltage floorplan design with optimal voltage assignment, in: Proceedings of the 2009 International Symposium on Physical Design, 2009, pp. 13–18.\nMa, 2011, Msv-driven floorplanning, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30, 1152, 10.1109\u002FTCAD.2011.2131890\nJ. Hu, Y. Shin, N. Dhanwada, R. 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