[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"_public_publisher_byId_2c727e60-f02c-43fb-8221-7839852b080c":3,"_public_publication_all{\"sortAscending\":false,\"sortField\":\"updateTime\",\"page\":0,\"size\":10,\"facet\":true,\"searchKey\":\"publisherId:2c727e60-f02c-43fb-8221-7839852b080c,\"}":19},{"code":4,"data":5,"meta":9},"SUCCESS",{"id":6,"createTime":7,"updateTime":7,"relativeEntities":8,"slug":9,"properties":10,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":16,"manageAffiliations":17,"indexDatabases":18,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},"2c727e60-f02c-43fb-8221-7839852b080c","2023-12-23T19:04:47.440+00:00",[],null,{"title":11},{"EN":12},"Proceedings. IEEE Asia-Pacific Conference on ASIC,","PUBLISHER","PENDING",0,[],[],[],{"meta":20,"data":22},{"total":21},"86",[23,81,160,238,331,404,491,579,665,745],{"id":24,"createTime":25,"updateTime":26,"relativeEntities":27,"slug":28,"properties":29,"entityType":42,"verifyStatus":43,"verifyTime":44,"verifyNote":45,"languages":9,"translateLanguages":46,"viewCount":15,"primaryUrl":48,"fullTextUrl":49,"authors":50,"publicationType":67,"publisherRelationship":68,"citationCount":9,"citationInfo":9,"publishDate":9,"publishYear":9,"citationAnalyzeStatus":14,"lastCitationAnalyze":9,"indexDatabases":79,"openAccess":9,"references":9,"isForceReanalyzing":80},"6465b796-a7bf-4795-83df-77e11f109c1e","2023-12-23T19:26:58.700+00:00","2026-09-11T07:20:35.420+00:00",[],"A-0-18-spl-mu-m-CMOS-offset-PLL-upconversion-modulation-loop-IC-for-DCS-1800-transmitter",{"abstract":30,"title":32,"keywords":35,"references":38,"doi":40},{"EN":31},"A DCS-1800 offset-PLL upconversion modulation loop IC, which is fabricated in a 0.18-\u002Fspl mu\u002Fm CMOS technology, is presented in this paper. This IC operates at 2.8 V supply voltage with a current consumption of 36 mA. The measured r.m.s. and peak phase errors of the GMSK transmission signal are 1.6 and 4 degree, respectively. It is shown that such circuit can be implemented in a CMOS process with current dissipation and performance comparable to BiCMOS commercial products. The advantages of an upconversion modulation loop and the design issues of IQ modulators are also described in this paper.",{"EN":33,"VI":34},"A 0.18-\u002Fspl mu\u002Fm CMOS offset-PLL upconversion modulation loop IC for DCS-1800 transmitter","IC vòng điều chế biến đổi lên offset-PLL bằng CMOS 0,18-μm cho máy phát DCS-1800",{"EN":36,"VI":37},"CMOS integrated circuits,Transmitters,Voltage-controlled oscillators,Phase frequency detector,CMOS technology,CMOS process,Transceivers,BiCMOS integrated circuits,Radio frequency,Phase modulation","mạch tích hợp CMOS, máy phát, bộ dao động điều khiển bằng điện áp, bộ tách pha - tần số, công nghệ CMOS, quy trình CMOS, máy thu phát, mạch tích hợp BiCMOS, tần số vô tuyến, điều chế pha",{"VOID":39},"10.1109\u002F4.748179\n10.1109\u002FCICC.2000.852738\n1997, Digital cellular telecommunications system (Phase 2+); Mobile Station (MS) conformance specification; Part 1: Conformance specification (GSM 11.10-1 version 6.0.0 Release 1997), European Telecommunications Standards Institute Copyright\nrazavi, 1999, RF transmitter architectures circuits, CICC Dig Tech Papers, 197\nwu, 1997, A 2V 100MHz CMOS vector modulator, ISSCC Digest of Technical Papers, 80\n10.1109\u002F4.643666\n0, HD155121F, Hitachi Semiconductor datasheet",{"VOID":41},"10.1109\u002FAPASIC.2002.1031593","PUBLICATION","VERIFIED","2024-12-06T18:30:13.319+00:00","Auto Verify",[47],"VI","https:\u002F\u002Fieeexplore.ieee.org\u002Fabstract\u002Fdocument\u002F1031593\u002F","https:\u002F\u002Fieeexplore.ieee.org\u002Fstamp\u002Fstamp.jsp?tp=&arnumber=1031593",[51],{"id":52,"sortIndex":15,"researcher":9,"roles":53,"affiliations":55,"properties":64,"displayName":66,"givenName":9,"familyName":9},"8842547d-4ac8-4897-94a1-a07e967b2613",[54],"AUTHOR",[56],{"id":57,"sortIndex":15,"affiliation":58,"properties":9},"51557cfb-e67e-49c0-b8dc-30272d0f3419",{"id":57,"createTime":9,"updateTime":9,"relativeEntities":59,"slug":9,"properties":60,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":63,"statistic":9},[],{"title":61},{"VI":62},"SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan",[],{"title":65},{"VI":66},"J.-M. Hsu","ARTICLE",{"url":48,"publisher":69,"properties":76},{"id":6,"createTime":7,"updateTime":7,"relativeEntities":70,"slug":9,"properties":71,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":73,"manageAffiliations":74,"indexDatabases":75,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},[],{"title":72},{"EN":12},[],[],[],{"pages":77},{"VOID":78},"307-310",[],false,{"id":82,"createTime":83,"updateTime":84,"relativeEntities":85,"slug":86,"properties":87,"entityType":42,"verifyStatus":43,"verifyTime":100,"verifyNote":45,"languages":9,"translateLanguages":101,"viewCount":15,"primaryUrl":102,"fullTextUrl":103,"authors":104,"publicationType":67,"publisherRelationship":148,"citationCount":9,"citationInfo":9,"publishDate":9,"publishYear":9,"citationAnalyzeStatus":14,"lastCitationAnalyze":9,"indexDatabases":159,"openAccess":9,"references":9,"isForceReanalyzing":80},"0cf53d14-e40f-428c-b07a-da9c7b9bf455","2023-12-23T19:23:34.755+00:00","2026-09-08T12:15:13.350+00:00",[],"A-64-bit-parallel-CMOS-adder-for-high-performance-processors",{"abstract":88,"title":90,"keywords":93,"references":96,"doi":98},{"EN":89},"A fast 64 bit parallel binary adder for high performance microprocessors and DSP processors is described. It is implemented in UMC 2.5 V 0.25 \u002Fspl mu\u002Fm 1-poly 5-metal CMOS technology. A new adder architecture with four stages of dynamic logic is proposed, based on the modification of Kogge and Stone algorithm. Efficiently using dynamic compound gates, clock-delayed dynamic logic and FET scaling technique, the new adder architecture achieved good performance. The addition latency is 700 ps, 20% faster than that of the conventional architecture adder. The area of the adder is 0.16 mm\u002Fsup 2\u002F, similar to that of the conventional one.",{"EN":91,"VI":92},"A 64 bit parallel CMOS adder for high performance processors","Bộ cộng CMOS song song 64 bit cho các bộ xử lý hiệu suất cao",{"EN":94,"VI":95},"CMOS process,Adders,CMOS technology,Computer architecture,Microelectronics,Digital signal processing,CMOS logic circuits,Clocks,Delay,FETs","quy trình CMOS, bộ cộng, công nghệ CMOS, kiến trúc máy tính, vi điện tử, xử lý tín hiệu số, mạch logic CMOS, xung nhịp, độ trễ, FET",{"VOID":97},"10.1109\u002FTC.1982.1675982\nhennessy, 1999, Computer Organization & Design the Hardware\u002FSoftware Interface\n10.1109\u002F4.236178\n10.1109\u002FTC.1973.5009159\n10.1109\u002FARITH.2001.930129\n10.1109\u002F12.165399\nlindkwist, 1995, Dynamic CMOS Circuit Techniques for Delay and Power Reduction in Parallel Adder, 16th Conference on Advanced Research in VLSI, 121\nbernstein, 1998, High Speed CMOS Design Styles\nnaffziger, 1996, A Sub-Nanosecond O.5um 64b Adder Design, IEEE International Solid-State Circuits Conference, 362\n10.1109\u002F4.340419\nkazu, 1985, FET Scaling in Domino CMOS Gates, IEEE Journal of Solid-State Circuits, sc 20, 1067\n10.1109\u002F4.509867",{"VOID":99},"10.1109\u002FAPASIC.2002.1031568","2025-02-18T19:55:47.215+00:00",[47],"https:\u002F\u002Fieeexplore.ieee.org\u002Fabstract\u002Fdocument\u002F1031568\u002F","https:\u002F\u002Fieeexplore.ieee.org\u002Fstamp\u002Fstamp.jsp?tp=&arnumber=1031568",[105,120,134],{"id":106,"sortIndex":15,"researcher":9,"roles":107,"affiliations":108,"properties":117,"displayName":119,"givenName":9,"familyName":9},"57111985-0884-4d43-91fc-6d27afe4492e",[54],[109],{"id":110,"sortIndex":15,"affiliation":111,"properties":9},"5beb3a09-a3fd-40d1-8916-f1e466070c1c",{"id":110,"createTime":9,"updateTime":9,"relativeEntities":112,"slug":9,"properties":113,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":116,"statistic":9},[],{"title":114},{"VI":115},"Microelectronics Center, Harbin Institute of Technology, Harbin, China",[],{"title":118},{"VI":119},"Sun Xu-guang",{"id":121,"sortIndex":122,"researcher":9,"roles":123,"affiliations":124,"properties":131,"displayName":133,"givenName":9,"familyName":9},"5aea073d-e997-4dca-9cec-1f9552cb8fad",1,[54],[125],{"id":110,"sortIndex":15,"affiliation":126,"properties":9},{"id":110,"createTime":9,"updateTime":9,"relativeEntities":127,"slug":9,"properties":128,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":130,"statistic":9},[],{"title":129},{"VI":115},[],{"title":132},{"VI":133},"Mao Zhi-gang",{"id":135,"sortIndex":136,"researcher":9,"roles":137,"affiliations":138,"properties":145,"displayName":147,"givenName":9,"familyName":9},"e31c661d-01fb-49d1-8fa2-68f7bf7a804d",2,[54],[139],{"id":110,"sortIndex":15,"affiliation":140,"properties":9},{"id":110,"createTime":9,"updateTime":9,"relativeEntities":141,"slug":9,"properties":142,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":144,"statistic":9},[],{"title":143},{"VI":115},[],{"title":146},{"VI":147},"Lai Feng-chang",{"url":102,"publisher":149,"properties":156},{"id":6,"createTime":7,"updateTime":7,"relativeEntities":150,"slug":9,"properties":151,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":153,"manageAffiliations":154,"indexDatabases":155,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},[],{"title":152},{"EN":12},[],[],[],{"pages":157},{"VOID":158},"205-208",[],{"id":161,"createTime":162,"updateTime":163,"relativeEntities":164,"slug":165,"properties":166,"entityType":42,"verifyStatus":43,"verifyTime":179,"verifyNote":45,"languages":9,"translateLanguages":9,"viewCount":15,"primaryUrl":180,"fullTextUrl":181,"authors":182,"publicationType":67,"publisherRelationship":224,"citationCount":9,"citationInfo":9,"publishDate":9,"publishYear":9,"citationAnalyzeStatus":235,"lastCitationAnalyze":236,"indexDatabases":237,"openAccess":9,"references":9,"isForceReanalyzing":80},"6fab2adb-af9a-4e64-815d-3714699627cd","2023-12-23T19:26:27.061+00:00","2026-07-22T12:01:33.918+00:00",[],"Design-and-implementation-of-a-scalable-fast-Fourier-transform-core",{"abstract":167,"title":169,"gsPaper":171,"keywords":173,"references":175,"doi":177},{"EN":168},"A novel approach for scalable length Fast Fourier Transform (FFT) in single Processing Element (single PE) architecture has been developed. The scalable length FFT design meets the different lengths requirement of FFT operation in an OFDM system. An efficient mechanism, named Interleaved Rotated Data Allocation (IRDA), to replace the multiple-port memory with a single-port memory has also been proposed. Using a single-port memory instead of multiple-port memory makes the design more area efficient.",{"EN":170},"Design and implementation of a scalable fast Fourier transform core",{"VOID":172},"[]",{"EN":174},"Fast Fourier transforms,Costs,OFDM,Silicon,Hardware,Fourier transforms,Signal processing,Digital signal processing,Lungs,Digital video broadcasting",{"VOID":176},"1997, Framing Structure Channel Coding and Modulation for Digital Terrestrial Television\n10.1109\u002FISCAS.2001.922322\nthomson, 1992, Introduction to parallel algorithms and architectures Arrays Tree Hypercube, 731\n2000, Digital audio broadcasting (DAB) to mobile portable and fixed receivers\n10.1109\u002FCICC.1998.694922\noppenheim, 1999, Discrete Time Signal Processing\n10.1109\u002F82.142032\n2000, Fast Fourier Transforming apparatus and method variable bit reverse circuit inverse Fast Fourier Transforming apparatus and method and OFDM receiver and transmitter\nvan nee, 2000, OFDM for Wireless Multimedia Communications",{"VOID":178},"10.1109\u002FAPASIC.2002.1031590","2024-06-25T19:12:32.738+00:00","https:\u002F\u002Fieeexplore.ieee.org\u002Fabstract\u002Fdocument\u002F1031590\u002F","https:\u002F\u002Fieeexplore.ieee.org\u002Fstamp\u002Fstamp.jsp?tp=&arnumber=1031590",[183,198,211],{"id":184,"sortIndex":15,"researcher":9,"roles":185,"affiliations":186,"properties":195,"displayName":197,"givenName":9,"familyName":9},"739834cc-d423-4686-96a9-5162f61b14fb",[54],[187],{"id":188,"sortIndex":15,"affiliation":189,"properties":9},"ed1fac83-518c-4b2c-8c61-1b1c84013078",{"id":188,"createTime":9,"updateTime":9,"relativeEntities":190,"slug":9,"properties":191,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":194,"statistic":9},[],{"title":192},{"VI":193},"VLSl Signal Processing Group Department of Electronlcs Engineering, National Chiao Tung University, Hsinchu, Taiwan",[],{"title":196},{"VI":197},"Cheng-Han Sung",{"id":199,"sortIndex":122,"researcher":9,"roles":200,"affiliations":201,"properties":208,"displayName":210,"givenName":9,"familyName":9},"1a55a3b1-2a3e-4ad1-ad30-46403d454651",[54],[202],{"id":188,"sortIndex":15,"affiliation":203,"properties":9},{"id":188,"createTime":9,"updateTime":9,"relativeEntities":204,"slug":9,"properties":205,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":207,"statistic":9},[],{"title":206},{"VI":193},[],{"title":209},{"VI":210},"Kun-Bin Lee",{"id":212,"sortIndex":136,"researcher":9,"roles":213,"affiliations":214,"properties":221,"displayName":223,"givenName":9,"familyName":9},"a0544cb6-3158-4252-a5ce-ef2597df3c34",[54],[215],{"id":188,"sortIndex":15,"affiliation":216,"properties":9},{"id":188,"createTime":9,"updateTime":9,"relativeEntities":217,"slug":9,"properties":218,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":220,"statistic":9},[],{"title":219},{"VI":193},[],{"title":222},{"VI":223},"Chein-Wei Jen",{"url":180,"publisher":225,"properties":232},{"id":6,"createTime":7,"updateTime":7,"relativeEntities":226,"slug":9,"properties":227,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":229,"manageAffiliations":230,"indexDatabases":231,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},[],{"title":228},{"EN":12},[],[],[],{"pages":233},{"VOID":234},"295-298","ERROR_IN_GET_PLATFORM_ID","2026-07-22T12:01:33.917+00:00",[],{"id":239,"createTime":240,"updateTime":241,"relativeEntities":242,"slug":243,"properties":244,"entityType":42,"verifyStatus":43,"verifyTime":255,"verifyNote":45,"languages":9,"translateLanguages":9,"viewCount":15,"primaryUrl":256,"fullTextUrl":257,"authors":258,"publicationType":67,"publisherRelationship":300,"citationCount":136,"citationInfo":311,"publishDate":9,"publishYear":9,"citationAnalyzeStatus":14,"lastCitationAnalyze":313,"indexDatabases":314,"openAccess":9,"references":315,"isForceReanalyzing":80},"4da5a6b9-a5ab-4ad7-800d-6388944ab8df","2023-12-23T19:05:25.287+00:00","2026-04-27T09:00:13.291+00:00",[],"A-CMOS-current-mode-band-pass-filter-with-small-chip-area",{"abstract":245,"title":247,"gsPaper":249,"keywords":251,"doi":253},{"EN":246},"In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large area on an IC chip, being different from the conventional one. The proposed filter needs smaller area than the conventional one under the condition of Q > 2. The proposed circuit is simulated by SPICE to confirm its characteristics.",{"EN":248},"A CMOS current-mode band-pass filter with small chip area",{"VOID":250},"[\"10590087506400022456\"]",{"EN":252},"Band pass filters,Circuits,Passband,Q factor,Capacitors,Parasitic capacitance,CMOS technology,Permission,Transfer functions,Transconductance",{"VOID":254},"10.1109\u002FAPASIC.2002.1031520","2024-04-29T13:22:04.672+00:00","https:\u002F\u002Fieeexplore.ieee.org\u002Fabstract\u002Fdocument\u002F1031520\u002F","https:\u002F\u002Fieeexplore.ieee.org\u002Fstamp\u002Fstamp.jsp?tp=&arnumber=1031520",[259,274,287],{"id":260,"sortIndex":15,"researcher":9,"roles":261,"affiliations":262,"properties":271,"displayName":273,"givenName":9,"familyName":9},"46310819-4375-4a71-9ae3-e0f121956ed8",[54],[263],{"id":264,"sortIndex":15,"affiliation":265,"properties":9},"582c73be-c639-4281-8692-e0e74f02314b",{"id":264,"createTime":9,"updateTime":9,"relativeEntities":266,"slug":9,"properties":267,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":270,"statistic":9},[],{"title":268},{"VI":269},"Tokyo University of Science, Chiba, Japan",[],{"title":272},{"VI":273},"Y. Maruyama",{"id":275,"sortIndex":122,"researcher":9,"roles":276,"affiliations":277,"properties":284,"displayName":286,"givenName":9,"familyName":9},"bb5b2a06-8791-44c4-a887-c8c12620f919",[54],[278],{"id":264,"sortIndex":15,"affiliation":279,"properties":9},{"id":264,"createTime":9,"updateTime":9,"relativeEntities":280,"slug":9,"properties":281,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":283,"statistic":9},[],{"title":282},{"VI":269},[],{"title":285},{"VI":286},"A. Hyogo",{"id":288,"sortIndex":136,"researcher":9,"roles":289,"affiliations":290,"properties":297,"displayName":299,"givenName":9,"familyName":9},"d0be3236-0bad-4b61-8c49-db9d44175fe1",[54],[291],{"id":264,"sortIndex":15,"affiliation":292,"properties":9},{"id":264,"createTime":9,"updateTime":9,"relativeEntities":293,"slug":9,"properties":294,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":296,"statistic":9},[],{"title":295},{"VI":269},[],{"title":298},{"VI":299},"K. Sekine",{"url":256,"publisher":301,"properties":308},{"id":6,"createTime":7,"updateTime":7,"relativeEntities":302,"slug":9,"properties":303,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":305,"manageAffiliations":306,"indexDatabases":307,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},[],{"title":304},{"EN":12},[],[],[],{"pages":309},{"VOID":310},"13-16",{"total":136,"publishYear":9,"statisticByYear":312},{"2008":122},"2026-04-27T09:00:13.290+00:00",[],[316,319,322,325,328],{"id":9,"text":317,"url":9,"identifiers":318},"toshinobu, 0, A Current Gain Tuning Circuit with Bulk-Source Voltage Control, Proceedings of The 2000 Electronics Society of IEICE, c 12 21, 101",{},{"id":9,"text":320,"url":9,"identifiers":321},"nobuo, 0, High Frequency Low Voltage Current Mode Analog Integrable Filters, Proceedings of the 1998Bipolar \u002F BiCMOS Circuits and Technology Meeting, 47",{},{"id":9,"text":323,"url":9,"identifiers":324},"smith, 1996, Low Voltage Integrator for High Frequency Application, IEEE Trans CAS-II, 43, 39",{},{"id":9,"text":326,"url":9,"identifiers":327},"yuhki, 0, A Digitally Programmable CMOS Current-Mode Universal Biquad Filter, Proceedings of 2001 IEEJ International Analog VLSI Workshop, 97",{},{"id":9,"text":329,"url":9,"identifiers":330},"toshinobu, 0, 2V-500MHz CMOS Continuous-Time Current-Mode Filter Using the Gate-Source Capacitance of the MOSFET, ISPACS'99, 493",{},{"id":332,"createTime":333,"updateTime":334,"relativeEntities":335,"slug":336,"properties":337,"entityType":42,"verifyStatus":43,"verifyTime":334,"verifyNote":45,"languages":9,"translateLanguages":9,"viewCount":15,"primaryUrl":348,"fullTextUrl":349,"authors":350,"publicationType":67,"publisherRelationship":392,"citationCount":9,"citationInfo":9,"publishDate":9,"publishYear":9,"citationAnalyzeStatus":14,"lastCitationAnalyze":9,"indexDatabases":403,"openAccess":9,"references":9,"isForceReanalyzing":80},"203af179-e708-4602-b247-b571322da70b","2023-12-23T19:28:32.021+00:00","2025-02-21T21:16:13.492+00:00",[],"A-low-power-Reed-Solomon-decoder-for-STM-16-optical-communications",{"abstract":338,"title":340,"keywords":342,"references":344,"doi":346},{"EN":339},"In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2 K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The (255,239) RS decoder is implemented by 0.25 \u002Fspl mu\u002Fm CMOS 1P5M standard cells with gate counts of 32.9 K and area of 2.03 mm\u002Fsup 2\u002F. Simulation results show our approach can work successfully at the data rate of 2.5-Gbps and achieve 80% reduction of power dissipation on the average.",{"EN":341},"A low-power Reed-Solomon decoder for STM-16 optical communications",{"EN":343},"Reed-Solomon codes,Decoding,Polynomials,Optical fiber communication,Equations,Energy consumption,Proposals,Computational modeling,Circuit simulation,Power dissipation",{"VOID":345},"seki, 2001, Single-chip 10.7 Gb\u002Fs FEC CODEC LSI using time-multiplexed RS de-coder, IEEE Custom Integrated Circuits Conference, 289\nmceliece, 1988, The Decoding of Reed-Solomon Codes, The Telecommunications and Data Acquisition Progress Report 42–95, 153\nchang, 1994, A high speed Reed-Solomon CODEC chip using look-forward architecture, IEEE Asia-Pacific Conference on Circuits and Systems, 212\n10.1137\u002F0109020",{"VOID":347},"10.1109\u002FAPASIC.2002.1031604","https:\u002F\u002Fieeexplore.ieee.org\u002Fabstract\u002Fdocument\u002F1031604\u002F","https:\u002F\u002Fieeexplore.ieee.org\u002Fstamp\u002Fstamp.jsp?tp=&arnumber=1031604",[351,366,379],{"id":352,"sortIndex":15,"researcher":9,"roles":353,"affiliations":354,"properties":363,"displayName":365,"givenName":9,"familyName":9},"ad3d5817-758f-4fa4-acd5-88f26dca56dd",[54],[355],{"id":356,"sortIndex":15,"affiliation":357,"properties":9},"6d57e81c-ee04-43c1-a21e-e2f0a4f8a212",{"id":356,"createTime":9,"updateTime":9,"relativeEntities":358,"slug":9,"properties":359,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":362,"statistic":9},[],{"title":360},{"VI":361},"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.",[],{"title":364},{"VI":365},"Hsie-Chia Chang",{"id":367,"sortIndex":122,"researcher":9,"roles":368,"affiliations":369,"properties":376,"displayName":378,"givenName":9,"familyName":9},"b91a517a-7ec4-4f90-b852-62d992aad250",[54],[370],{"id":356,"sortIndex":15,"affiliation":371,"properties":9},{"id":356,"createTime":9,"updateTime":9,"relativeEntities":372,"slug":9,"properties":373,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":375,"statistic":9},[],{"title":374},{"VI":361},[],{"title":377},{"VI":378},"Chien-Ching Lin",{"id":380,"sortIndex":136,"researcher":9,"roles":381,"affiliations":382,"properties":389,"displayName":391,"givenName":9,"familyName":9},"120f7612-4244-4961-b910-6abf3a478ffe",[54],[383],{"id":356,"sortIndex":15,"affiliation":384,"properties":9},{"id":356,"createTime":9,"updateTime":9,"relativeEntities":385,"slug":9,"properties":386,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":388,"statistic":9},[],{"title":387},{"VI":361},[],{"title":390},{"VI":391},"Chen-Yi Lee",{"url":348,"publisher":393,"properties":400},{"id":6,"createTime":7,"updateTime":7,"relativeEntities":394,"slug":9,"properties":395,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":397,"manageAffiliations":398,"indexDatabases":399,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},[],{"title":396},{"EN":12},[],[],[],{"pages":401},{"VOID":402},"351-354",[],{"id":405,"createTime":406,"updateTime":407,"relativeEntities":408,"slug":409,"properties":410,"entityType":42,"verifyStatus":43,"verifyTime":407,"verifyNote":45,"languages":9,"translateLanguages":9,"viewCount":15,"primaryUrl":421,"fullTextUrl":422,"authors":423,"publicationType":67,"publisherRelationship":479,"citationCount":9,"citationInfo":9,"publishDate":9,"publishYear":9,"citationAnalyzeStatus":14,"lastCitationAnalyze":9,"indexDatabases":490,"openAccess":9,"references":9,"isForceReanalyzing":80},"2dc22df2-10ff-4903-b23c-a419b3479c12","2023-12-23T19:07:50.952+00:00","2025-02-21T20:27:22.587+00:00",[],"A-high-throughput-low-cost-AES-cipher-chip",{"abstract":411,"title":413,"keywords":415,"references":417,"doi":419},{"EN":412},"We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 \u002Fspl mu\u002Fm CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5 K gates.",{"EN":414},"A high-throughput low-cost AES cipher chip",{"EN":416},"Elliptic curve cryptography,Hardware,CMOS technology,Clocks,Application specific integrated circuits,Table lookup,Laboratories,Costs,Internet,Communication system security",{"VOID":418},"kuo, 2001, Architectural optimization for a 1.82 Gbits\u002Fsec VLSI implementation of the AES Rijndael algorithm, Proceedings of Cryptographic Hardware and Embedded Systems (CHES 2000), 10.1007\u002F3-540-44709-1_6\nrijmen, 0, Efficient implementation of the Rijndael S-box\npeterson, 1972, Error-Correcting Codes\n10.1109\u002FATS.2001.990265\n10.1109\u002F92.931230\n10.1145\u002F359340.359342\ngaj, 2000, Comparison of the hardware performance of the AES candidates using reconfigurable hardware, Proc 3rd AES Candidate Conference\nweaver, 2000, A comparison of the AES candidates amenability to FPGA implementation, Proc 3rd AES Candidate Conference\nweeks, 2000, Hard-ware performance simulations of round 2 Advanced Encryption Standard algorithm, Proc 3rd AES Candidate Conference\nli, 2001, A Gbps AES cipher, Dept Computer Science\n2001, National Institute of Standards and Technology (NIST), Advanced Encryption Standard (AES)\n1999, National Institute of Standards and Technology (NIST), Data Encryption Standard (DES)\nichikawa, 2000, Hardware evaluation of the AES finalists, Proc 3rd AES Candidate Conference",{"VOID":420},"10.1109\u002FAPASIC.2002.1031538","https:\u002F\u002Fieeexplore.ieee.org\u002Fabstract\u002Fdocument\u002F1031538\u002F","https:\u002F\u002Fieeexplore.ieee.org\u002Fstamp\u002Fstamp.jsp?tp=&arnumber=1031538",[424,439,452,465],{"id":425,"sortIndex":15,"researcher":9,"roles":426,"affiliations":427,"properties":436,"displayName":438,"givenName":9,"familyName":9},"d22956cd-ab58-48fc-95f1-75530b5b70ef",[54],[428],{"id":429,"sortIndex":15,"affiliation":430,"properties":9},"1d44aa26-b922-4705-8fc8-d33569d919f8",{"id":429,"createTime":9,"updateTime":9,"relativeEntities":431,"slug":9,"properties":432,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":435,"statistic":9},[],{"title":433},{"VI":434},"Laboratory for Reliable Computing, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan",[],{"title":437},{"VI":438},"Tsung-Fu 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Huang",{"id":466,"sortIndex":467,"researcher":9,"roles":468,"affiliations":469,"properties":476,"displayName":478,"givenName":9,"familyName":9},"a12b4161-0f7d-4a7a-b8e1-f59785a55c4f",3,[54],[470],{"id":429,"sortIndex":15,"affiliation":471,"properties":9},{"id":429,"createTime":9,"updateTime":9,"relativeEntities":472,"slug":9,"properties":473,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":475,"statistic":9},[],{"title":474},{"VI":434},[],{"title":477},{"VI":478},"Cheng-Wen Wu",{"url":421,"publisher":480,"properties":487},{"id":6,"createTime":7,"updateTime":7,"relativeEntities":481,"slug":9,"properties":482,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":484,"manageAffiliations":485,"indexDatabases":486,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},[],{"title":483},{"EN":12},[],[],[],{"pages":488},{"VOID":489},"85-88",[],{"id":492,"createTime":493,"updateTime":494,"relativeEntities":495,"slug":496,"properties":497,"entityType":42,"verifyStatus":43,"verifyTime":494,"verifyNote":45,"languages":9,"translateLanguages":9,"viewCount":15,"primaryUrl":508,"fullTextUrl":509,"authors":510,"publicationType":67,"publisherRelationship":567,"citationCount":9,"citationInfo":9,"publishDate":9,"publishYear":9,"citationAnalyzeStatus":14,"lastCitationAnalyze":9,"indexDatabases":578,"openAccess":9,"references":9,"isForceReanalyzing":80},"aca87add-9787-4211-b1ca-929c57c48501","2023-12-23T19:26:22.452+00:00","2025-02-21T01:15:48.632+00:00",[],"A-novel-block-equalization-design-for-wireless-communication-with-ISI-and-Rayleigh-fading-channels",{"abstract":498,"title":500,"keywords":502,"references":504,"doi":506},{"EN":499},"In this paper, a novel block channel equalization design for wireless communication over mobile radio channels with both inter-symbol interference (ISI) and Rayleigh fading is presented. The proposed design consists of a matched filter, a channel estimator and a block decision feedback equalizer (BDFE). The channel estimator, which is based on a revised RLS algorithm, adopts a semi-blind approach. The estimated channel impulse response h(n) is used later in both matched filtering and the BDFE update. The BDFE actually consists of a noise whitener and a maximum-likelihood block detector followed by a symbol detector. The filter coefficients of the BDFE are calculated subject to the Cholesky factorization and are updated once for each data block. Various wireless channel models, covering ISI and Rayleigh fading, have been simulated to demonstrate the effectiveness of the proposed equalization scheme. Based on this scheme, a novel systolic array design is next developed. The derived equalizer design features a highly parallel, hardware efficient and scalable design. Implementation results on a Xilinx XCV600 FPGA indicate an up-to-3-million symbols per second processing rate at 35 MHz working frequency.",{"EN":501},"A novel block equalization design for wireless communication with ISI and Rayleigh fading channels",{"EN":503},"Wireless communication,Intersymbol interference,Fading,Rayleigh channels,Matched filters,Detectors,Land mobile radio,Decision feedback equalizers,Resonance light scattering,Filtering",{"VOID":505},"10.1109\u002F78.622950\n10.1109\u002F78.771048\n10.1109\u002F49.737631\n10.1109\u002F78.845924\nhwang, 2000, A novel FPGA design of a wireless block transmission channel equalizer, Proc APASIC, 119\n10.1109\u002F78.317867\n10.1109\u002F49.363140\n10.1109\u002F18.312157",{"VOID":507},"10.1109\u002FAPASIC.2002.1031589","https:\u002F\u002Fieeexplore.ieee.org\u002Fabstract\u002Fdocument\u002F1031589\u002F","https:\u002F\u002Fieeexplore.ieee.org\u002Fstamp\u002Fstamp.jsp?tp=&arnumber=1031589",[511,526,539,552],{"id":512,"sortIndex":15,"researcher":9,"roles":513,"affiliations":514,"properties":523,"displayName":525,"givenName":9,"familyName":9},"490e20e6-864d-4273-970f-e3cc72cd932f",[54],[515],{"id":516,"sortIndex":15,"affiliation":517,"properties":9},"c6c82b6d-8305-4a8b-9ebc-892d47bd6d62",{"id":516,"createTime":9,"updateTime":9,"relativeEntities":518,"slug":9,"properties":519,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":522,"statistic":9},[],{"title":520},{"VI":521},"Department of Electronic Engineering., National Yunlin University of Science and Technology, Yulin, China",[],{"title":524},{"VI":525},"Yin-Tsung Hwang",{"id":527,"sortIndex":122,"researcher":9,"roles":528,"affiliations":529,"properties":536,"displayName":538,"givenName":9,"familyName":9},"58009128-36fd-43e9-af83-3bb0d78629e3",[54],[530],{"id":516,"sortIndex":15,"affiliation":531,"properties":9},{"id":516,"createTime":9,"updateTime":9,"relativeEntities":532,"slug":9,"properties":533,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":535,"statistic":9},[],{"title":534},{"VI":521},[],{"title":537},{"VI":538},"Jing-Yi Liu",{"id":540,"sortIndex":136,"researcher":9,"roles":541,"affiliations":542,"properties":549,"displayName":551,"givenName":9,"familyName":9},"fe26d57a-edb8-439a-8917-37b163063bad",[54],[543],{"id":516,"sortIndex":15,"affiliation":544,"properties":9},{"id":516,"createTime":9,"updateTime":9,"relativeEntities":545,"slug":9,"properties":546,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":548,"statistic":9},[],{"title":547},{"VI":521},[],{"title":550},{"VI":551},"Chi-Cheng Han",{"id":553,"sortIndex":467,"researcher":9,"roles":554,"affiliations":555,"properties":564,"displayName":566,"givenName":9,"familyName":9},"a0afd2e4-4b81-4848-8ee2-553e7c7d8911",[54],[556],{"id":557,"sortIndex":15,"affiliation":558,"properties":9},"94d74698-65e5-4095-89d0-790170e7f2cf",{"id":557,"createTime":9,"updateTime":9,"relativeEntities":559,"slug":9,"properties":560,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":563,"statistic":9},[],{"title":561},{"VI":562},"Department of Electrical Engineering, National Chung Cheng University, Chiayi, Taiwan",[],{"title":565},{"VI":566},"Chien-Hsing Wu",{"url":508,"publisher":568,"properties":575},{"id":6,"createTime":7,"updateTime":7,"relativeEntities":569,"slug":9,"properties":570,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":572,"manageAffiliations":573,"indexDatabases":574,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},[],{"title":571},{"EN":12},[],[],[],{"pages":576},{"VOID":577},"291-294",[],{"id":580,"createTime":581,"updateTime":582,"relativeEntities":583,"slug":584,"properties":585,"entityType":42,"verifyStatus":43,"verifyTime":582,"verifyNote":45,"languages":9,"translateLanguages":9,"viewCount":15,"primaryUrl":596,"fullTextUrl":597,"authors":598,"publicationType":67,"publisherRelationship":653,"citationCount":9,"citationInfo":9,"publishDate":9,"publishYear":9,"citationAnalyzeStatus":14,"lastCitationAnalyze":9,"indexDatabases":664,"openAccess":9,"references":9,"isForceReanalyzing":80},"8380be7b-9205-4b78-b15f-74912d428d5d","2023-12-23T19:28:06.446+00:00","2025-02-20T09:19:07.164+00:00",[],"A-high-performance-function-generator-for-multiplier-based-arithmetic-operations",{"abstract":586,"title":588,"keywords":590,"references":592,"doi":594},{"EN":587},"An automatic hardware generator is developed for computing multiplier-based arithmetic functions. The generator can produce Verilog codes of parallel multipliers\u002Fmultiplier-accumulator\u002Finner product calculator and their corresponding test fixture files for pre-layout simulation. The irregular connection of the Wallace tree in the parallel multiplier is optimized in order to reduce the critical path delay. In addition to the conventional 3:2 counter that is usually included in standard cell library, our generator can select other different compression elements that are designed using the full-custom approach based on pass-transistor logic. Thus, our multiplier generator combines the advantages of three basic design methodologies: high-level synthesis, cell-based design, full-custom design along with area\u002Ftime optimization.",{"EN":589},"A high performance function generator for multiplier-based arithmetic operations",{"EN":591},"Signal generators,Arithmetic,Hardware design languages,Testing,Fixtures,Computational modeling,Delay,Counting circuits,Libraries,Logic design",{"VOID":593},"10.1109\u002F4.509865\n10.1109\u002F4.52161\nhsiao, 2000, Efficient Synthesizer for Generation for Fast Parallel Multipliers, IEE Proceedings on Computers and Digital Techniques, 147, 49, 10.1049\u002Fip-cdt:20000164\n10.1109\u002F92.386228\n10.1109\u002FISSCC.1993.280071\n10.1109\u002F92.238424",{"VOID":595},"10.1109\u002FAPASIC.2002.1031599","https:\u002F\u002Fieeexplore.ieee.org\u002Fabstract\u002Fdocument\u002F1031599\u002F","https:\u002F\u002Fieeexplore.ieee.org\u002Fstamp\u002Fstamp.jsp?tp=&arnumber=1031599",[599,614,627,640],{"id":600,"sortIndex":15,"researcher":9,"roles":601,"affiliations":602,"properties":611,"displayName":613,"givenName":9,"familyName":9},"dcb1f55e-db01-4b82-a996-73ff961c2f61",[54],[603],{"id":604,"sortIndex":15,"affiliation":605,"properties":9},"876d512f-f06e-49ce-a5a0-e385a8258d59",{"id":604,"createTime":9,"updateTime":9,"relativeEntities":606,"slug":9,"properties":607,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":610,"statistic":9},[],{"title":608},{"VI":609},"Department of Computer Science Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan",[],{"title":612},{"VI":613},"Tso-Bing Juang",{"id":615,"sortIndex":122,"researcher":9,"roles":616,"affiliations":617,"properties":624,"displayName":626,"givenName":9,"familyName":9},"f68ffc2d-9a7c-47bb-8f14-36feeb8e9392",[54],[618],{"id":604,"sortIndex":15,"affiliation":619,"properties":9},{"id":604,"createTime":9,"updateTime":9,"relativeEntities":620,"slug":9,"properties":621,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":623,"statistic":9},[],{"title":622},{"VI":609},[],{"title":625},{"VI":626},"Jeng-Hsin Jan",{"id":628,"sortIndex":136,"researcher":9,"roles":629,"affiliations":630,"properties":637,"displayName":639,"givenName":9,"familyName":9},"4c29fe54-a2f9-4752-bcb5-5eeea388b64a",[54],[631],{"id":604,"sortIndex":15,"affiliation":632,"properties":9},{"id":604,"createTime":9,"updateTime":9,"relativeEntities":633,"slug":9,"properties":634,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":636,"statistic":9},[],{"title":635},{"VI":609},[],{"title":638},{"VI":639},"Ming-Yu Tsai",{"id":641,"sortIndex":467,"researcher":9,"roles":642,"affiliations":643,"properties":650,"displayName":652,"givenName":9,"familyName":9},"4bc19d31-9b59-4711-8d2c-046008f8d6eb",[54],[644],{"id":604,"sortIndex":15,"affiliation":645,"properties":9},{"id":604,"createTime":9,"updateTime":9,"relativeEntities":646,"slug":9,"properties":647,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":649,"statistic":9},[],{"title":648},{"VI":609},[],{"title":651},{"VI":652},"Shen-Fu Hsiao",{"url":596,"publisher":654,"properties":661},{"id":6,"createTime":7,"updateTime":7,"relativeEntities":655,"slug":9,"properties":656,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":658,"manageAffiliations":659,"indexDatabases":660,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},[],{"title":657},{"EN":12},[],[],[],{"pages":662},{"VOID":663},"331-334",[],{"id":666,"createTime":667,"updateTime":668,"relativeEntities":669,"slug":670,"properties":671,"entityType":42,"verifyStatus":43,"verifyTime":685,"verifyNote":45,"languages":9,"translateLanguages":686,"viewCount":15,"primaryUrl":687,"fullTextUrl":688,"authors":689,"publicationType":67,"publisherRelationship":733,"citationCount":9,"citationInfo":9,"publishDate":9,"publishYear":9,"citationAnalyzeStatus":14,"lastCitationAnalyze":9,"indexDatabases":744,"openAccess":9,"references":9,"isForceReanalyzing":80},"fb6031da-2e40-4cab-a882-d617a3806298","2023-12-23T19:29:30.785+00:00","2025-02-19T07:01:26.898+00:00",[],"All-digital-CDMA-upstream-transmitter-and-baseband-VLSI-design-of-head-end-receiver-for-upstream-cable-networks",{"abstract":672,"title":675,"keywords":678,"references":681,"doi":683},{"EN":673,"VI":674},"This paper presents an all digital DS-CDMA upstream transmitter arid a head-end baseband receiver for upstream cable\u002FHFC networks. The upstream transmitter supports frequency agility of the carrier, QPSK and QAM constellations up to 64QAM, variable symbol rates from 160kchip\u002Fs to 5.12Mchip\u002Fs increasing by power of two, and direct-digital up-conversion to achieve accurate amplitude and phase of modulation. The transmitter consists of pulse shaping filter, half-band filter, cascaded integrator-comb (CIC) filter, and inverse SINC filter. The all digital head-end baseband receiver supports programmable quadrature amplitude modulation up to 64QAM. Fast timing and carrier recovery algorithms are adopted for burst mode transmission. Code acquisition can be achieved within 2 symbols, and the carrier acquisition can be achieved within 31 symbols. All digital timing recovery is designed with \u002Fspl plusmn\u002F200ppm symbol timing offset tolerance and the carrier recovery can compensate \u002Fspl plusmn\u002F100ppm of carrier frequency offset.","Bài báo này trình bày một bộ phát DS-CDMA hoàn toàn kỹ thuật số cho đường lên và một bộ thu cơ sở đầu cuối cho các mạng cáp\u002FHFC. Bộ phát đường lên hỗ trợ tính linh hoạt tần số của sóng mang, các chòm sao QPSK và QAM lên đến 64QAM, tốc độ ký hiệu biến đổi từ 160kchip\u002Fs đến 5.12Mchip\u002Fs, tăng gấp đôi theo lũy thừa, và chuyển đổi lên số trực tiếp để đạt được độ chính xác trong biên độ và pha điều chế. Bộ phát bao gồm bộ lọc định hình xung, bộ lọc bán băng, bộ lọc tích hợp-cắt (CIC) chuỗi, và bộ lọc SINC ngược. Bộ thu cơ sở đầu cuối hoàn toàn kỹ thuật số hỗ trợ điều chế biên độ vuông có thể lập trình lên đến 64QAM. Các thuật toán phục hồi thời gian và sóng mang nhanh được áp dụng cho truyền tải chế độ burst. Việc định vị mã có thể đạt được trong vòng 2 ký hiệu, và việc định vị sóng mang có thể đạt được trong vòng 31 ký hiệu. Phục hồi thời gian hoàn toàn kỹ thuật số được thiết kế với khả năng dung sai sai lệch thời gian ký hiệu \u002Fspl plusmn\u002F200ppm và phục hồi sóng mang có thể bù trừ \u002Fspl plusmn\u002F100ppm của sai lệch tần số sóng mang.",{"EN":676,"VI":677},"All digital CDMA upstream transmitter and baseband VLSI design of head-end receiver for upstream cable networks","Bộ phát DS-CDMA kỹ thuật số hoàn toàn và thiết kế VLSI cơ sở của bộ thu đầu cuối cho mạng cáp đầu lên",{"EN":679,"VI":680},"Multiaccess communication,Transmitters,Baseband,Very large scale integration,Filters,Timing,Frequency,Quadrature amplitude modulation,Hybrid fiber coaxial cables,Quadrature phase shift keying","Giao tiếp đa truy cập, Bộ phát, Cơ sở, Tích hợp quy mô rất lớn, Bộ lọc, Thời gian, Tần số, Điều chế biên độ vuông, Cáp quang lai đồng trục, Khóa pha điều chế điều chế biên độ vuông",{"VOID":682},"iong, 1990, A cdma based bi-directional conmmunicat.ion system for hybrid fiber-coax catv networks, IEEE Trans on Broadcastinq, 43\nfarrow, 1988, A contiuously variable digital delay element, Proceeding IEEE Intern Syrnp Circuits Syst Espoo, 2g42\nshnon, 1977, Noncohercnt pseudonoise code tracking perfOrtnrtllce of spread spcctrurn receiver, IEEE Trnnsactions on Commnnicaiions, 25\nkamperman, 1994, Design of a all digital direct-sequence sprcad-spectrt1111 receiver, PIMRC\n10.1109\u002F35.400609\ncaourax, 1999, Fast currier recovery for burst-mode coherent demodulation using feedforward phase and frequency estiInatioll techniques, Proc IEEE Electrical Computer Engineering Conf",{"VOID":684},"10.1109\u002FAPASIC.2002.1031609","2025-02-06T00:09:42.379+00:00",[47],"https:\u002F\u002Fieeexplore.ieee.org\u002Fabstract\u002Fdocument\u002F1031609\u002F","https:\u002F\u002Fieeexplore.ieee.org\u002Fstamp\u002Fstamp.jsp?tp=&arnumber=1031609",[690,705,720],{"id":691,"sortIndex":15,"researcher":9,"roles":692,"affiliations":693,"properties":702,"displayName":704,"givenName":9,"familyName":9},"ca93994a-aa38-409f-8f37-e54d1ee58db9",[54],[694],{"id":695,"sortIndex":15,"affiliation":696,"properties":9},"19d2018f-b8a7-4424-a770-336fa0320248",{"id":695,"createTime":9,"updateTime":9,"relativeEntities":697,"slug":9,"properties":698,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":701,"statistic":9},[],{"title":699},{"VI":700},"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan",[],{"title":703},{"VI":704},"Keng-Yi Su",{"id":706,"sortIndex":122,"researcher":9,"roles":707,"affiliations":708,"properties":717,"displayName":719,"givenName":9,"familyName":9},"1dd421af-03b5-46cc-8c41-37cc9e464bd3",[54],[709],{"id":710,"sortIndex":15,"affiliation":711,"properties":9},"fee0972a-b0f1-4504-a699-cf147d00a02e",{"id":710,"createTime":9,"updateTime":9,"relativeEntities":712,"slug":9,"properties":713,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":716,"statistic":9},[],{"title":714},{"VI":715},"Trendchip Technologies Corporation, Hsinchu, Taiwan",[],{"title":718},{"VI":719},"Muh-Tain Shieu",{"id":721,"sortIndex":136,"researcher":9,"roles":722,"affiliations":723,"properties":730,"displayName":732,"givenName":9,"familyName":9},"8dcb01d7-b6d5-41af-a485-06b798303bfa",[54],[724],{"id":695,"sortIndex":15,"affiliation":725,"properties":9},{"id":695,"createTime":9,"updateTime":9,"relativeEntities":726,"slug":9,"properties":727,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":729,"statistic":9},[],{"title":728},{"VI":700},[],{"title":731},{"VI":732},"Chorng-Kuang Wang",{"url":687,"publisher":734,"properties":741},{"id":6,"createTime":7,"updateTime":7,"relativeEntities":735,"slug":9,"properties":736,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":738,"manageAffiliations":739,"indexDatabases":740,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},[],{"title":737},{"EN":12},[],[],[],{"pages":742},{"VOID":743},"371-374",[],{"id":746,"createTime":747,"updateTime":748,"relativeEntities":749,"slug":750,"properties":751,"entityType":42,"verifyStatus":43,"verifyTime":748,"verifyNote":45,"languages":9,"translateLanguages":9,"viewCount":15,"primaryUrl":762,"fullTextUrl":763,"authors":764,"publicationType":67,"publisherRelationship":806,"citationCount":9,"citationInfo":9,"publishDate":9,"publishYear":9,"citationAnalyzeStatus":14,"lastCitationAnalyze":9,"indexDatabases":817,"openAccess":9,"references":9,"isForceReanalyzing":80},"010e8a2c-0ac0-46eb-afc5-d84de9e7fc1e","2023-12-23T19:18:06.428+00:00","2025-02-17T21:49:35.910+00:00",[],"A-staged-carry-save-adder-array-for-Montgomery-modular-multiplication",{"abstract":752,"title":754,"keywords":756,"references":758,"doi":760},{"EN":753},"In this paper, an efficient VLSI architecture to compute the n-bit Montgomery modular multiplication is proposed. By using the staged carry save adder (CSA) array, the computation cycles of addition reduced by about 3n\u002F8. In addition, we apply the switch unit to save 2Q-2 registers from the traditional Q-bit CSA. Compare with the original method, the total clock cycles can be reduced by 68% in the case of n=1024 and Q=512 bits.",{"EN":755},"A staged carry-save-adder array for Montgomery modular multiplication",{"EN":757},"Hardware,Clocks,Costs,Switches,Public key cryptography,Cities and towns,Computer architecture,Data security,Modems,Digital signatures",{"VOID":759},"swartzlander, 1990, Computer Arithmetic, i\nkaya koc, 1994, High-Speed RSA Implementation, RSA Laboratories\ngai, 1996, A Systolic Linear Array for Modular Multiplication, ASIC 1996 2nd International Conference on, 171\nkaya koc, 1995, RSA Hardware Implementation, RSA Laboratories\nguo, 1998, A Novel Digital-Serial Systolic Array for Modular Multiplication, Proceedings of the 1998 IEEE International Symposium on, 2, 177\nkoren, 1993, Computer arithmetic algorithms\n10.1109\u002FARITH.1999.762831\n10.2307\u002F2007970\nknuth, 1981, The art of computer progranuning: Seminumerical Algorithms, 2\n10.1109\u002FICSICT.1998.785937\n10.1145\u002F359340.359342",{"VOID":761},"10.1109\u002FAPASIC.2002.1031541","https:\u002F\u002Fieeexplore.ieee.org\u002Fabstract\u002Fdocument\u002F1031541\u002F","https:\u002F\u002Fieeexplore.ieee.org\u002Fstamp\u002Fstamp.jsp?tp=&arnumber=1031541",[765,780,793],{"id":766,"sortIndex":15,"researcher":9,"roles":767,"affiliations":768,"properties":777,"displayName":779,"givenName":9,"familyName":9},"3e1971ed-9dcb-491f-8907-d23e38bb1689",[54],[769],{"id":770,"sortIndex":15,"affiliation":771,"properties":9},"79f2d153-5868-45da-8cf0-1e124efbc19e",{"id":770,"createTime":9,"updateTime":9,"relativeEntities":772,"slug":9,"properties":773,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":776,"statistic":9},[],{"title":774},{"VI":775},"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan",[],{"title":778},{"VI":779},"Jhing-Fa Wang",{"id":781,"sortIndex":122,"researcher":9,"roles":782,"affiliations":783,"properties":790,"displayName":792,"givenName":9,"familyName":9},"1aed6fcd-1c76-4695-8de4-b613e7a4f165",[54],[784],{"id":770,"sortIndex":15,"affiliation":785,"properties":9},{"id":770,"createTime":9,"updateTime":9,"relativeEntities":786,"slug":9,"properties":787,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":789,"statistic":9},[],{"title":788},{"VI":775},[],{"title":791},{"VI":792},"Po-Chuan Lin",{"id":794,"sortIndex":136,"researcher":9,"roles":795,"affiliations":796,"properties":803,"displayName":805,"givenName":9,"familyName":9},"2eaa0468-c3d2-4153-9682-47ee4dac9209",[54],[797],{"id":770,"sortIndex":15,"affiliation":798,"properties":9},{"id":770,"createTime":9,"updateTime":9,"relativeEntities":799,"slug":9,"properties":800,"entityType":9,"verifyStatus":9,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":9,"url":9,"parentIds":802,"statistic":9},[],{"title":801},{"VI":775},[],{"title":804},{"VI":805},"Ping-Kun Chiu",{"url":762,"publisher":807,"properties":814},{"id":6,"createTime":7,"updateTime":7,"relativeEntities":808,"slug":9,"properties":809,"entityType":13,"verifyStatus":14,"verifyTime":9,"verifyNote":9,"languages":9,"translateLanguages":9,"viewCount":15,"subjectFields":811,"manageAffiliations":812,"indexDatabases":813,"url":9,"thumbnailPath":9,"statistic":9,"gsStatistic":9,"type":9,"analyzePriority":9},[],{"title":810},{"EN":12},[],[],[],{"pages":815},{"VOID":816},"97-100",[]]