Bridging fault modeling and simulation for deep submicron CMOS ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 8 - Trang 941-953 - 2002
Tóm tắt
Testing bridging faults in deep submicron CMOS digital ICs faces new problems because of pushing the technology limits. The growing dispersion of process parameters makes it hard to use conventional bridging fault models for high-quality testing. A new fault model is proposed to account for bridging faults in a way that is independent of electrical parameters and provides a significant coverage metric. Conditions are defined to ensure that (under steady-state conditions) either a fault is detected by a test sequence or it will not give rise to errors for any other input, independently of the actual values of IC parameters. Such a fault model has been implemented in a simulator and validated over combinational benchmarks.
Từ khóa
#Semiconductor device modeling #Circuit faults #Integrated circuit testing #Logic testing #CMOS technology #Electrical fault detection #Fault detection #CMOS logic circuits #Performance evaluation #Logic devicesTài liệu tham khảo
10.1109/TEST.1991.519712
10.1145/337292.337779
10.1109/TEST.1999.805784
10.1109/TEST.1999.805783
10.1109/12.660170
10.1109/CICC.1993.590783
10.1109/VTEST.1999.766675
10.1023/A:1008223826585
10.1109/ATS.1997.643976
10.1007/BF00134730
10.1145/337292.337601
10.1109/VTEST.1995.512635
10.1109/ICVD.1995.512135
10.1109/2.803640
10.1109/EDTC.1996.494116
10.1109/43.240087
10.1007/BF00136074
10.1109/CICC.1992.591298
10.1109/TEST.1993.470613
10.1109/TEST.1993.470717
10.1109/43.536713
10.1109/TEST.1993.470718
sentovich, 1992, SIS A system for sequential circuit synthesis
10.1109/TEST.1999.805800
10.1109/TEST.1999.805615
10.1109/TEST.1996.557118
sachdev, 1999, defect detection with transient current testing and its potential for deep sub-micron cmos ics, Proc IEEE Int Test Conf, 204
miller, 1999, <formula><tex>$i_{ddq}$</tex></formula> testing in deep submicron integrated circuits, Proc IEEE Int Test Conf, 724
maxwell, 1998, current ratios: a self-scaling technique for production <formula><tex>$i_{ddq}$</tex></formula> testing, Proc IEEE Int Test Conf, 738
10.1109/VTEST.2000.843876
10.1109/43.79505
10.1007/BF00133502
10.1109/TEST.1990.114102
10.1109/TEST.1991.519521
10.1109/TEST.1998.743133
10.1109/TEST.1997.639695
10.1109/5.843000
10.1109/54.785836
kruseman, 1999, transient current testing in 0.25 <formula> <tex>$\mu\hbox{m}$</tex></formula> cmos devices, Proc IEEE Int Test Conf, 47
10.1007/BF00134011
10.1109/EDTC.1996.494359
jiang, 1999, statistical formulation for dynamic <formula> <tex>$i_{dd}$</tex></formula> lest, Proc lEEE Int Test Conf, 57
10.1109/TEST.1998.743175
10.1109/2.803637
0, CAO-VLSI Tools BDD Library Manual
10.1109/TC.1986.1676819
10.1109/ISCAS.1993.692949
10.1109/VTEST.1991.208132
10.1109/MDT.1985.294793
brglez, 1985, a neutral netlist of 10 combinational bench-mark circuits and a target translator in fortran, Proc IEEE Int Symp Circuits and Systems, 663