An instruction-level energy model for embedded VLIW architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 9 - Trang 998-1010 - 2002
Tóm tắt
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power consumption information during either an instruction-level simulation or power-oriented scheduling at compile time. The analytical model takes into account several software-level parameters (such as instruction ordering, pipeline stall probability, and instruction cache miss probability) as well as microarchitectural-level ones (such as pipeline stage power consumption per instruction) providing an efficient pipeline-aware instruction-level power estimation, whose accuracy is very close to those given by RT or gate-level simulations. The problem of instruction-level power characterization of a K-issue VLIW processor is O(N/sup 2K/) where N is the number of operations in the ISA and K is the number of parallel instructions composing the very long instruction. One of the advantages of the proposed model consists of reducing the complexity of the characterization problem to O(K/spl times/N/sup 2/). The proposed model has been used to characterize a four-issue VLIW core with a six-stage pipeline.
Từ khóa
#VLIW #Energy consumption #Engines #Processor scheduling #Analytical models #Pipeline processing #Application software #Microarchitecture #Instruction sets #Digital signal processingTài liệu tham khảo
10.1109/DAC.2002.1012747
10.1007/978-1-4615-5685-5_15
10.1145/337292.337436
10.1109/92.831433
brooks, 2000, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA, 83
10.1145/337292.337436
10.1109/LPE.1995.482457
10.1109/LPE.1994.573194
10.1109/40.888701
10.1109/92.335012
lee, 1997, power analysis and minimization techniques for embedded dsp software, IEEE Transactions VLSI Syst, 5, 123, 10.1109/92.555992
10.1109/ICCD.1998.727070
10.1109/LPD.1999.750419
klass, 1998, modeling inter-instruction energy effects in a digital signal processor, Power-Driven Microarchitecture Workshop in Conjunction With Int Symp Computer Architecture
10.1109/92.386219
li, 1998, a framework for estimating and minimizing energy dissipation of embedded hw/sw systems, DAC-28 ACM/IEEE Design Automation Conf, 188
10.1109/92.845897
10.1109/43.736181
10.1109/ICCAD.2000.896522
sami, 2000, Instruction-level power estimation for embedded VLIW cores, Proceedings of the Eighth International Workshop on Hardware/Software Codesign CODES 2000 (IEEE Cat No 00TH8518) HSC, 34
10.1145/337292.337786
10.1109/92.532037
10.1109/92.335013
10.1109/LPE.1996.542726
10.1109/43.736182
10.1109/5.371964
hennessy, 1996, Computer Architecture A Quantitative Approach
mehta, 1997, Techniques for low energy software, Proceedings of 1997 International Symposium on Low Power Electronics and Design LPE, 72, 10.1145/263272.263286
10.1109/LPD.1999.750403
10.1109/5.558718
10.1007/978-1-4615-5685-5_10
corporaal, 0, Microprocessor Architectures From VLIW to TTA
kamble, 1997, Analytical energy dissipation models for low power caches, Proceedings of 1997 International Symposium on Low Power Electronics and Design LPE, 143